SN74LVC574APWR
Public Unreviewedby Ray
Texas Instruments Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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README
markdownSN74LVC574APWR
Texas Instruments · Flip Flops · TSSOP-20
SN74LVC574APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low output enable (OE). When low, the eight Q outputs are enabled; when high, all Q outputs are placed in the high-impedance (3-state) condition. Does not affect internal flip-flop operation. Tie to VCC through a pullup during power-up/down to guarantee Hi-Z. |
| 2 | 1D | input | Data input to flip-flop 1. Sampled on the rising edge of CLK and transferred to output 1Q. Inputs accept voltages up to 5.5 V. |
| 3 | 2D | input | Data input to flip-flop 2. Sampled on the rising edge of CLK and transferred to output 2Q. |
| 4 | 3D | input | Data input to flip-flop 3. Sampled on the rising edge of CLK and transferred to output 3Q. |
| 5 | 4D | input | Data input to flip-flop 4. Sampled on the rising edge of CLK and transferred to output 4Q. |
| 6 | 5D | input | Data input to flip-flop 5. Sampled on the rising edge of CLK and transferred to output 5Q. |
| 7 | 6D | input | Data input to flip-flop 6. Sampled on the rising edge of CLK and transferred to output 6Q. |
| 8 | 7D | input | Data input to flip-flop 7. Sampled on the rising edge of CLK and transferred to output 7Q. |
| 9 | 8D | input | Data input to flip-flop 8. Sampled on the rising edge of CLK and transferred to output 8Q. |
| 10 | GND | power_in | Ground reference (0 V). Common return for VCC and all input/output signals. |
| 11 | CLK | input | Clock input common to all eight flip-flops. Data on D inputs is transferred to Q outputs on the rising edge (positive transition) of CLK. Minimum pulse width 3.3 ns at VCC = 3.3 V; fmax up to 150 MHz. |
| 12 | 8Q | tri_state | 3-state output of flip-flop 8. Reflects last clocked value of 8D when OE is low; Hi-Z when OE is high. Drive capability of ±24 mA at VCC = 3 V. |
| 13 | 7Q | tri_state | 3-state output of flip-flop 7. Reflects last clocked value of 7D when OE is low; Hi-Z when OE is high. |
| 14 | 6Q | tri_state | 3-state output of flip-flop 6. Reflects last clocked value of 6D when OE is low; Hi-Z when OE is high. |
| 15 | 5Q | tri_state | 3-state output of flip-flop 5. Reflects last clocked value of 5D when OE is low; Hi-Z when OE is high. |
| 16 | 4Q | tri_state | 3-state output of flip-flop 4. Reflects last clocked value of 4D when OE is low; Hi-Z when OE is high. |
| 17 | 3Q | tri_state | 3-state output of flip-flop 3. Reflects last clocked value of 3D when OE is low; Hi-Z when OE is high. |
| 18 | 2Q | tri_state | 3-state output of flip-flop 2. Reflects last clocked value of 2D when OE is low; Hi-Z when OE is high. |
| 19 | 1Q | tri_state | 3-state output of flip-flop 1. Reflects last clocked value of 1D when OE is low; Hi-Z when OE is high. |
| 20 | VCC | power_in | Positive supply voltage, 1.65 V to 3.6 V operating range (SN74LVC574A). Decouple with a local bypass capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Ordering variants
Same part, different packaging or reel option.
SN74LVC574APWRSN74LVC574APWRAPWTSN74LVC574APWRADWSN74LVC574APWRADWRSN74LVC574APWRADBRSN74LVC574APWRADGVRSN74LVC574APWRANSRSN74LVC574APWRANSN74LVC574APWRARGYRSN74LVC574APWRAGQNRSN74LVC574APWRAZQNRSN74LVC574APWRFKSN74LVC574APWRJSN74LVC574APWRW
CAD (KiCad official)
- Symbol:
SN74LVC574APWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
sn74lvc574apwr.step |
267 KB | You want the bare part, or you mark your own boards. |
sn74lvc574apwr-etched.step |
2.8 MB | You want the part with SN74LVC574APWR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 726 faces against 327 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
e6aad666cf80743a, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).