STM8S007C8T6TR from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NRST	bidirectional	Active-low reset pin; its electrical limits are given in the NRST pin characteristics table (Table 39).
2	PA1/OSCIN	bidirectional	Port A1 multiplexed with the resonator/crystal oscillator input, with speed option O1 (up to 2 MHz).
3	PA2/OSCOUT	bidirectional	Port A2 multiplexed with the resonator/crystal oscillator output, with speed option O1 (up to 2 MHz).
4	VSSIO_1	power_in	I/O ground connection for the first group of I/O pins.
5	VSS	power_in	Digital ground connection.
6	VCAP	passive	Connection for the 1.8 V regulator external capacitor, whose requirements are given in section 9.3.1.
7	VDD	power_in	Digital power supply, operating from 2.95 V to 5.5 V.
8	VDDIO_1	power_in	I/O power supply for the first group of I/O pins.
9	PA3/TIM2_CH3	bidirectional	Port A3 with TIM2 channel 3 as default alternate function, and TIM3_CH1 available when the AFR1 remap option is active.
10	PA4/UART1_RX	bidirectional	Port A4 with UART1 receive, high sink capable; its default state is controlled by the ROM bootloader and it returns to floating before bootloader exit.
11	PA5/UART1_TX	bidirectional	Port A5 with UART1 transmit, high sink capable.
12	PA6/UART1_CK	bidirectional	Port A6 with UART1 synchronous clock, high sink capable.
13	VDDA	power_in	Analog power supply for the ADC.
14	VSSA	power_in	Analog ground for the ADC.
15	PB7/AIN7	bidirectional	Port B7 with analog input 7 of the 10-bit ADC.
16	PB6/AIN6	bidirectional	Port B6 with analog input 6 of the 10-bit ADC.
17	PB5/AIN5	bidirectional	Port B5 with analog input 5 of the 10-bit ADC, and I2C_SDA available after the AFR6 remap option.
18	PB4/AIN4	bidirectional	Port B4 with analog input 4 of the 10-bit ADC, and I2C_SCL available after the AFR6 remap option.
19	PB3/AIN3	bidirectional	Port B3 with analog input 3 of the 10-bit ADC, and TIM1_ETR available after the AFR5 remap option.
20	PB2/AIN2	bidirectional	Port B2 with analog input 2 of the 10-bit ADC, and TIM1_CH3N available after the AFR5 remap option.
21	PB1/AIN1	bidirectional	Port B1 with analog input 1 of the 10-bit ADC, and TIM1_CH2N available after the AFR5 remap option.
22	PB0/AIN0	bidirectional	Port B0 with analog input 0 of the 10-bit ADC, and TIM1_CH1N available after the AFR5 remap option.
23	PE7/AIN8	bidirectional	Port E7 with analog input 8 of the 10-bit ADC.
24	PE6/AIN9	bidirectional	Port E6 with analog input 9 of the 10-bit ADC.
25	PE5/SPI_NSS	bidirectional	Port E5 with SPI master/slave select function.
26	PC1/TIM1_CH1	bidirectional	Port C1 with TIM1 channel 1, high sink capable.
27	PC2/TIM1_CH2	bidirectional	Port C2 with TIM1 channel 2, high sink capable.
28	PC3/TIM1_CH3	bidirectional	Port C3 with TIM1 channel 3, high sink capable.
29	PC4/TIM1_CH4	bidirectional	Port C4 with TIM1 channel 4, high sink capable.
30	PC5/SPI_SCK	bidirectional	Port C5 with SPI clock, high sink capable.
31	VSSIO_2	power_in	I/O ground connection for the second group of I/O pins.
32	VDDIO_2	power_in	I/O power supply for the second group of I/O pins.
33	PC6/SPI_MOSI	bidirectional	Port C6 with SPI master out / slave in, high sink capable.
34	PC7/SPI_MISO	bidirectional	Port C7 with SPI master in / slave out, high sink capable.
35	PG0	bidirectional	Port G0 general-purpose I/O with speed option O1 (up to 2 MHz).
36	PG1	bidirectional	Port G1 general-purpose I/O with speed option O1 (up to 2 MHz).
37	PE3/TIM1_BKIN	bidirectional	Port E3 with TIM1 break input.
38	PE2/I2C_SDA	bidirectional	Port E2 with I2C data as a true open-drain pin (no protection diode to VDD), limited to 2 MHz slope.
39	PE1/I2C_SCL	bidirectional	Port E1 with I2C clock as a true open-drain pin (no protection diode to VDD), limited to 2 MHz slope.
40	PE0/CLK_CCO	bidirectional	Port E0 with configurable clock output, high sink capable.
41	PD0/TIM3_CH2	bidirectional	Port D0 with TIM3 channel 2 and high sink capability; TIM1_BKIN and CLK_CCO are available via AFR3 and AFR2 remap options.
42	PD1/SWIM	bidirectional	Port D1 with the SWIM single-wire debug data interface, high sink capable and in input pull-up during and after reset.
43	PD2/TIM3_CH1	bidirectional	Port D2 with TIM3 channel 1, high sink capable; TIM2_CH3 is available via the AFR1 remap option.
44	PD3/TIM2_CH2	bidirectional	Port D3 with TIM2 channel 2, high sink capable; ADC_ETR is available via the AFR0 remap option.
45	PD4/TIM2_CH1/BEEP	bidirectional	Port D4 with TIM2 channel 1, high sink capable; BEEP output is available via the AFR7 remap option.
46	PD5/UART3_TX	bidirectional	Port D5 with UART3 data transmit.
47	PD6/UART3_RX	bidirectional	Port D6 with UART3 data receive; its default state is controlled by the ROM bootloader and it returns to floating before bootloader exit.
48	PD7/TLI	bidirectional	Port D7 with top level interrupt input.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	Embedded Processors & Controllers
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage (including VDDA and VDDIO)	VDDx - VSS	-0.3		6.5	V		43
Input voltage on true open drain pins (PE1, PE2)	VIN			6.5	V	PE1, PE2; minimum printed as VSS - 0.3	43
Total current into VDD power lines (source)	IVDD			60	mA		45
Total current out of VSS ground lines (sink)	IVSS			60	mA		45
Output current sunk by any I/O and control pin	IIO			20	mA	sink	45
Output current source by any I/O and control pin	IIO			20	mA	source	45
Total output current sourced, devices with two VDDIO pins	ΣIIO			200	mA	two VDDIO pins	45
Total output current sunk, devices with one VSSIO pin	ΣIIO			80	mA	one VSSIO pin	45
Injected current on NRST pin	IINJ(PIN)	-4		4	mA		45
Total injected current (sum of all I/O and control pins)	ΣIINJ(PIN)	-20		20	mA		45
Storage temperature range	TSTG	-65		150	°C		45
Maximum junction temperature	TJ			150	°C		45
Internal CPU clock frequency	fCPU	0		24	MHz		46
Standard operating voltage	VDD/VDD_IO	2.95		5.5	V		46
CEXT: capacitance of external capacitor	CEXT	470		3300	nF	external capacitor on VCAP	46
ESR of external capacitor	ESR			0.3	ohm	At 1 MHz	46
ESL of external capacitor	ESL			15	nH		46
Power dissipation at TA = 85 °C for suffix 6	PD			443	mW	48-pin devices, output on eight standard ports, two high sink ports and two open drain ports simultaneously	46
Ambient temperature for 6 suffix version	TA	-40		85	°C	maximum power dissipation	46
Junction temperature range	TJ	-40		105	°C		46
Power-on reset threshold	VIT+	2.65	2.8	2.95	V		47
Brown-out reset threshold	VIT-	2.58	2.73	2.88	V		47
Reset release delay	tTEMP			1.7	ms	VDD rising	47
Supply current in run mode, code executed from Flash, HSE user ext. clock	IDD(RUN)		10.8	18	mA	VDD = 5 V, fCPU = fMASTER = 24 MHz	49
Supply current in run mode, code executed from Flash, HSI RC osc	IDD(RUN)		8.1	13.2	mA	VDD = 5 V, fCPU = fMASTER = 16 MHz	49
Supply current in run mode, code executed from RAM, HSE user ext. clock	IDD(RUN)		3.7	7.3	mA	VDD = 5 V, fCPU = fMASTER = 24 MHz	49
Supply current in wait mode, HSE user ext. clock	IDD(WFI)		1.8	4.7	mA	VDD = 5 V, fCPU = fMASTER = 24 MHz	51
Supply current in wait mode, HSE user ext. clock	IDD(WFI)		1.4	4.4	mA	VDD = 5 V, fCPU = fMASTER = 16 MHz	51
Supply current in wait mode, HSI RC osc	IDD(WFI)		1.2	1.6	mA	VDD = 5 V, fCPU = fMASTER = 16 MHz	51
Supply current in active halt mode, operating mode, LSI RC osc	IDD(AH)		200	260	µA	VDD = 5 V, TA -40 to 85 °C, MVR on, Flash operating mode, LSI RC oscillator (128 kHz)	52
Supply current in active halt mode, power-down mode, LSI RC osc	IDD(AH)		11	45	µA	VDD = 5 V, TA -40 to 85 °C, MVR off, Flash power-down mode, LSI RC oscillator (128 kHz)	52
Supply current in halt mode, Flash in power-down mode, HSI clock after wakeup	IDD(H)		6.5	35	µA	VDD = 5 V, TA -40 to 85 °C	53
Wakeup time active halt mode to run mode	tWU(AH)		1	2	µs	MVR voltage regulator on, Flash operating mode, HSI after wakeup	53
Reset release to bootloader vector fetch	tRESETBL			150	µs		54
User external clock source frequency	fHSE_ext	0		24	MHz		56
OSCIN input leakage current	ILEAK_HSE	-1		1	µA	VSS < VIN < VDD	56
Recommended load capacitance	C			20	pF		57
Accuracy of HSI oscillator	ACCHSI	-1		1	%	Trimmed by the CLK_HSITRIMR register for given VDD and TA conditions	58
Accuracy of HSI oscillator (factory calibrated)	ACCHSI	-5		5	%	VDD = 5 V, -40°C ≤ TA ≤ 85° C	58
HSI oscillator wakeup time including calibration	tsu(HSI)			1	µs		58
HSI oscillator power consumption	IDD(HSI)		170	250	µA		58
LSI oscillator wakeup time	tsu(LSI)			7	µs		59
Pull-up resistor	Rpu	30	55	80	kΩ	VDD = 5 V, VIN = VSS	61
Rise and fall time (10% - 90%), fast I/Os	tR, tF			20	ns	Load = 50 pF	61
Rise and fall time (10% - 90%), standard and high sink I/Os	tR, tF			125	ns	Load = 50 pF	61
Input leakage current, analog and digital	Ilkg	-1		1	µA	VSS ≤ VIN ≤ VDD	61
Analog input leakage current	Ilkg ana	-250		250	nA	VSS ≤ VIN ≤ VDD	61
Output low level with 8 pins sunk	VOL			2	V	IIO = 10 mA, VDD = 5 V	63
Output low level with 4 pins sunk	VOL			1	V	IIO = 4 mA, VDD = 3.3 V	63
Output high level with 8 pins sourced	VOH	2.8			V	IIO = 10 mA, VDD = 5 V	63
Output high level with 4 pins sourced	VOH	2.1			V	IIO = 4 mA, VDD = 3.3 V	63
NRST output low level voltage	VOL(NRST)			0.5	V	IOL = 2 mA	70
NRST pull-up resistor	RPU(NRST)	30	55	80	kΩ		70
SPI clock frequency, master mode	fSCK	0		10	MHz	Master mode	72
SPI clock frequency, slave mode	fSCK	0		6	MHz	Slave mode	72
Analog supply	VDDA	3		5.5	V		77
Operating voltage (all modes, execution/write/erase)	VDD	2.95		5.5	V	fCPU ≤ 16 MHz	60
Electrostatic discharge voltage (Human body model)	VESD(HBM)			2000	V	TA = 25°C, conforming to JESD22-A114, class A	81
Thermal resistance junction-ambient, LQFP 48 - 7 x 7 mm	ΘJA		57		°C/W	JEDEC JESD51-2, 4-layer PCB, natural convection	87

CAD (KiCad official)

Symbol: STM8S007C8T6TR
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: stm8s007c8t6tr-etched.step / stm8s007c8t6tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); stm8s007c8t6tr.step / stm8s007c8t6tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (93 pp, sha256 41316b954b059f1b, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

STM8S007C8T6TR

Verified STM8S007C8T6TR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README