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SN74LVTH273PWR

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Texas Instruments Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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SN74LVTH273PWR

Texas Instruments · Logic ICs · TSSOP-20

SN74LVTH273PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Direct-clear input: when low it forces all Q outputs low regardless of CLK or D (function table, page 2); it is buffered, and CLR high must be set up before CLK↑ per the timing requirements.
2 1Q output Flip-flop 1 true output, which follows 1D on the positive-going CLK edge and is cleared by CLR low.
3 1D input Individual data input to flip-flop 1; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown.
4 2D input Individual data input to flip-flop 2; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown.
5 2Q output Flip-flop 2 true output, which follows 2D on the positive-going CLK edge and is cleared by CLR low.
6 3Q output Flip-flop 3 true output, which follows 3D on the positive-going CLK edge and is cleared by CLR low.
7 3D input Individual data input to flip-flop 3; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown.
8 4D input Individual data input to flip-flop 4; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown.
9 4Q output Flip-flop 4 true output, which follows 4D on the positive-going CLK edge and is cleared by CLR low.
10 GND power_in Ground reference for the device.
11 CLK input Buffered positive-edge clock input; data is transferred to the Q outputs on the rising edge, with a maximum clock frequency of 150 MHz and minimum pulse duration of 3.3 ns.
12 5Q output Flip-flop 5 true output, which follows 5D on the positive-going CLK edge and is cleared by CLR low.
13 5D input Individual data input to flip-flop 5; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown.
14 6D input Individual data input to flip-flop 6; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown.
15 6Q output Flip-flop 6 true output, which follows 6D on the positive-going CLK edge and is cleared by CLR low.
16 7Q output Flip-flop 7 true output, which follows 7D on the positive-going CLK edge and is cleared by CLR low.
17 7D input Individual data input to flip-flop 7; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown.
18 8D input Individual data input to flip-flop 8; data must meet setup (2.3 ns at VCC 3.3 V) and hold (0 ns) times around CLK↑ and has bus hold to avoid external pullup/pulldown.
19 8Q output Flip-flop 8 true output, which follows 8D on the positive-going CLK edge and is cleared by CLR low.
20 VCC power_in Supply voltage, 2.7 V to 3.6 V per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 4.6 V 3
Input voltage range VI -0.5 7 V see Note 1 3
Voltage applied to any output in power-off state VO -0.5 7 V see Note 1 3
Voltage applied to any output in high state VO -0.5 V see Note 1; upper limit printed as VCC + 0.5 V 3
Current into any output in low state, SN74LVTH273 IO 128 mA 3
Current into any output in high state, SN74LVTH273 IO 64 mA see Note 2 3
Input clamp current IIK -50 mA VI < 0 3
Output clamp current IOK -50 mA VO < 0 3
Storage temperature range Tstg -65 150 °C 3
Supply voltage VCC 2.7 3.6 V SN74LVTH273 3
High-level input voltage VIH 2 V SN74LVTH273 3
Low-level input voltage VIL 0.8 V SN74LVTH273 3
Input voltage VI 5.5 V SN74LVTH273 3
High-level output current IOH -32 mA SN74LVTH273 3
Low-level output current IOL 64 mA SN74LVTH273 3
Input transition rise or fall rate Δt/Δv 10 ns/V 3
Operating free-air temperature TA -40 85 °C SN74LVTH273 3
High-level output voltage VOH 2.4 V VCC = 2.7 V, IOH = −8 mA 4
High-level output voltage VOH 2 V VCC = 3 V, IOH = −32 mA 4
Low-level output voltage VOL 0.2 V VCC = 2.7 V, IOL = 100 µA 4
Low-level output voltage VOL 0.5 V VCC = 2.7 V, IOL = 24 mA 4
Low-level output voltage VOL 0.4 V VCC = 2.7 V, IOL = 16 mA 4
Low-level output voltage VOL 0.55 V VCC = 3 V, IOL = 64 mA 4
Input clamp voltage VIK -1.2 V VCC = 2.7 V, II = −18 mA 4
Input current II 10 µA VCC = 0 or 3.6 V, VI = 5.5 V 4
Control inputs input current II -1 1 µA VCC = 3.6 V, VI = VCC or GND 4
Data inputs input current II 1 µA VCC = 3.6 V, VI = VCC 4
Data inputs input current II -5 µA VCC = 3.6 V, VI = 0 4
Power-off input/output current Ioff -100 100 µA VCC = 0, VI or VO = 0 to 4.5 V 4
Bus-hold sustaining current II(hold) 75 µA Data inputs, VCC = 3 V, VI = 0.8 V 4
Bus-hold sustaining current II(hold) -75 µA Data inputs, VCC = 3 V, VI = 2 V 4
Bus-hold maximum dynamic current ICC -750 500 µA VCC = 3.6 V, VI = 0 to 3.6 V (bus-hold maximum dynamic current, footnote ‡) 4
Supply current, outputs high ICC 0.19 mA VCC = 3.6 V, IO = 0, outputs high 4
Supply current, outputs low ICC 5 mA VCC = 3.6 V, IO = 0, VI = VCC or GND, outputs low 4
Supply current increase per input at TTL level ΔICC 0.2 mA VCC = 3 V to 3.6 V, one input at VCC − 0.6 V, others at VCC or GND 4
Clock frequency fclock 150 MHz 4
Pulse duration tw 3.3 ns VCC = 3.3 V ± 0.3 V 4
Setup time, data high or low before CLK↑ tsu 2.3 ns VCC = 3.3 V ± 0.3 V 4
Setup time, data high or low before CLK↑ tsu 2.7 ns VCC = 2.7 V 4
Setup time, CLR high before CLK↑ tsu 2.3 ns VCC = 3.3 V ± 0.3 V 4
Setup time, CLR high before CLK↑ tsu 2.7 ns VCC = 2.7 V 4
Hold time, data high or low after CLK↑ th 0 ns 4
Maximum clock frequency fmax 150 MHz CL = 50 pF 5
Propagation delay CLK to any Q (low-to-high) tPLH 1.7 3.2 4.9 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Propagation delay CLK to any Q (low-to-high) tPLH 5.5 ns VCC = 2.7 V, CL = 50 pF 5
Propagation delay CLK to any Q (high-to-low) tPHL 1.9 3.2 4.8 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Propagation delay CLK to any Q (high-to-low) tPHL 5.1 ns VCC = 2.7 V, CL = 50 pF 5
Propagation delay CLR to any Q (high-to-low) tPHL 1.6 2.7 4.3 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 5
Propagation delay CLR to any Q (high-to-low) tPHL 4.7 ns VCC = 2.7 V, CL = 50 pF 5
Package thermal impedance, PW package θJA 83 °C/W PW (TSSOP) package, per JESD 51-7 3

CAD (KiCad official)

  • Symbol: SN74LVTH273PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lvth273pwr-etched.step / sn74lvth273pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lvth273pwr.step / sn74lvth273pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 59c245f9eb91b841, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF