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CD4014BE
Public Made by Adomby adom
Texas Instruments Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4014BE
Texas Instruments · Shift Registers · DIP-16
CD4014BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PI-8 | input | Parallel data input for stage 8; inputs are protected by a CMOS protection network and limited to -0.5V to VDD+0.5V. |
| 2 | Q6 | output | Buffered Q output from stage 6 of the shift register. |
| 3 | Q8 | output | Buffered serial output from stage 8 of the shift register. |
| 4 | PI-4 | input | Parallel data input for stage 4, jammed in when PARALLEL/SERIAL CONTROL is high. |
| 5 | PI-3 | input | Parallel data input for stage 3, jammed in when PARALLEL/SERIAL CONTROL is high. |
| 6 | PI-2 | input | Parallel data input for stage 2, jammed in when PARALLEL/SERIAL CONTROL is high. |
| 7 | PI-1 | input | Parallel data input for stage 1, jammed in when PARALLEL/SERIAL CONTROL is high. |
| 8 | VSS | power_in | Ground (VSS) reference terminal for all voltages. |
| 9 | PARALLEL/SERIAL CONTROL | input | Low selects serial shift on the positive clock transition; high jams parallel inputs into the register on the positive clock transition. |
| 10 | CLOCK | input | Common clock input; the register advances on the positive clock transition, with a maximum clock frequency of 6 MHz at VDD=10V. |
| 11 | SERIAL IN | input | Serial data input to the first register stage, shifted in on the positive clock transition. |
| 12 | Q7 | output | Buffered Q output from stage 7 of the shift register. |
| 13 | PI-5 | input | Parallel data input for stage 5, jammed in when PARALLEL/SERIAL CONTROL is high. |
| 14 | PI-6 | input | Parallel data input for stage 6, jammed in when PARALLEL/SERIAL CONTROL is high. |
| 15 | PI-7 | input | Parallel data input for stage 7, jammed in when PARALLEL/SERIAL CONTROL is high. |
| 16 | VDD | power_in | Positive supply voltage, 3 V to 18 V recommended, absolute maximum -0.5V to +20V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4014BE - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4014be-etched.step/cd4014be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4014be.step/cd4014be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
078cf8019db65cb7, retrieved 2026-10-06, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).