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MCP3911A0-E

Public Made by Adom

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Microchip Tech Pre-ordered MCUs, QFN-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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MCP3911A0-E

Microchip Tech · Pre-ordered MCUs · QFN-20(4x4)

MCP3911A0-E from Microchip Tech, in a QFN-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CH0+ input Noninverting analog input for Channel 0; linear range is ±600 mV/GAIN with VREF = 1.2V, and absolute input is ±1V with no distortion (±2V without damage) relative to AGND.
2 CH0- input Inverting analog input for Channel 0; linear range is ±600 mV/GAIN with VREF = 1.2V, and absolute input is ±1V with no distortion (±2V without damage) relative to AGND.
3 CH1- input Inverting analog input for Channel 1; linear range is ±600 mV/GAIN with VREF = 1.2V, and absolute input is ±1V with no distortion (±2V without damage) relative to AGND.
4 CH1+ input Noninverting analog input for Channel 1; linear range is ±600 mV/GAIN with VREF = 1.2V, and absolute input is ±1V with no distortion (±2V without damage) relative to AGND.
5 AGND power_in Analog ground, return path for internal analog circuitry; must be connected to the same ground as DGND, preferably with a star connection.
6 REFIN+/OUT bidirectional Noninverting voltage reference input (external reference when VREFEXT = 1) and internal reference output (when VREFEXT = 0) with minimal drive capability, where a 0.1 µF ceramic capacitor is sufficient.
7 REFIN- input Inverting voltage reference input, connected to the external VREF- for a differential reference or directly to AGND for a single-ended or internal reference.
8 DGND power_in Digital ground, return path for internal digital circuitry; must be connected to the same ground as AGND, preferably with a star connection.
9 MDAT1 tri_state Modulator data output for Channel 1, high-impedance when its MODOUT bit is low and otherwise updated at the AMCLK frequency.
10 MDAT0 tri_state Modulator data output for Channel 0, high-impedance when its MODOUT bit is low and otherwise updated at the AMCLK frequency.
11 DR tri_state Active-low data ready pulse output, high-impedance when DR_HIZ = 0 (default) or driven high when DR_HIZ = 1; a 100 kΩ pull-up to DVDD is recommended when DR_HIZ = 0.
12 OSC1/CLKI input Oscillator crystal connection or external clock input.
13 OSC2 passive Oscillator crystal connection.
14 CS input Serial interface chip select input.
15 SCK input Serial interface clock input (SPI up to 20 MHz).
16 SDO output Serial interface data output (the pin table misprints it as 'Data Input').
17 SDI input Serial interface data input.
18 RESET input Active-low Schmitt-triggered master reset input that resets all registers to default and blocks communication while at DGND.
19 DVDD power_in Digital power supply, to be maintained between 2.7V and 3.6V with appropriate bypass capacitors.
20 AVDD power_in Analog power supply, to be maintained between 2.7V and 3.6V with appropriate bypass capacitors.
21 EP passive Exposed thermal pad, must be connected to AGND or left floating.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-20(4x4)
Category Embedded Processors & Controllers
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD VDD -0.3 4 V 3
Digital inputs and outputs w.r.t. AGND -0.3 4 V w.r.t. AGND 3
Analog input w.r.t. AGND -2 2 V w.r.t. AGND 3
VREF input w.r.t. AGND -0.6 V -0.6V to VDD + 0.6V 3
Storage temperature -65 150 °C 3
Ambient temp. with power applied -65 125 °C 3
Soldering temperature of leads 300 °C 10 seconds 3
ESD on all pins (HBM) 4 kV HBM 3
Resolution (No Missing Codes) 24 bits OSR = 256 or greater 3
Sampling Frequency fS(DMCLK) 1 4 MHz For maximum condition, BOOST[1:0] = 11 3
Output Data Rate fD(DRCLK) 4 125 ksps For maximum condition, BOOST[1:0] = 11, OSR = 32 3
Analog Input Absolute Voltage on CH0+, CH0-, CH1+, CH1- CH0+/- -1 1 V All analog input channels, measured to AGND 3
Offset Error VOS -2 0.2 2 mV Note 4 3
Gain Error GE -6 6 % Note 4 3
Differential Input Impedance G=1 ZIN 232 kΩ G = 1, proportional to 1/AMCLK 4
Differential Input Impedance G=32 ZIN 33 kΩ G = 32, proportional to 1/AMCLK 4
Signal-to-Noise and Distortion Ratio SINAD 92 94.5 dB Note 1 4
Total Harmonic Distortion THD -106.5 -103 dBc Includes the first 35 harmonics 4
Signal-to-Noise Ratio SNR 92 95 dB Note 1 4
Internal voltage reference tolerance VREF 1.176 1.2 1.224 V VREFEXT = 0, TA = +25°C only 5
Reference input capacitance 10 pF 5
Differential reference input voltage range (VREF+, VREF-) VREF 1.1 1.3 V VREFEXT = 1 5
Absolute Voltage on REFIN- Pin VREF- -0.1 0.1 V REFIN- should be connected to AGND when VREFEXT = 0 5
Master Clock Input Frequency Range fMCLK 20 MHz CLKEXT = 1 (Note 6) 5
Crystal Oscillator Operating Frequency Range fXTAL 1 20 MHz CLKEXT = 0 (Note 6) 5
Analog Master Clock AMCLK 16 MHz Note 6 5
Operating Voltage, Analog AVDD 2.7 3.6 V 5
Operating Voltage, Digital DVDD 2.7 3.6 V 5
Operating Current, Analog BOOST 00 IDD,A 1.5 2.3 mA BOOST[1:0] = 00 (Note 2) 5
Operating Current, Analog BOOST 01 IDD,A 1.8 2.8 mA BOOST[1:0] = 01 (Note 2) 5
Operating Current, Analog BOOST 10 IDD,A 2.5 3.5 mA BOOST[1:0] = 10 (Note 2) 5
Operating Current, Analog BOOST 11 IDD,A 4.4 6.25 mA BOOST[1:0] = 11 (Note 2) 5
Operating Current, Digital IDD,D 0.2 0.3 mA MCLK = 4 MHz, proportional to MCLK 6
Shutdown Current, Analog IDDS,A 1 µA AVDD pin only (Note 3) 6
Shutdown Current, Digital IDDS,D 1 µA DVDD pin only (Note 3) 6
Input Leakage Current ILI -1 1 µA CS = DVDD, VIN = DGND to DVDD 6
Output leakage Current ILO -1 1 µA CS = DVDD, VOUT = DGND or DVDD 6
Low-Level Output Voltage VOL 0.4 V IOL = +2.1 mA, DVDD = 3.3V 6
Internal Capacitance (all inputs and outputs) CINT 7 pF TA = +25°C, SCK = 1.0 MHz, DVDD = 3.3V (Note 1) 6
Serial Clock Frequency fSCK 20 MHz 7
CS Setup Time tCSS 25 ns 7
CS Hold Time tCSH 50 ns 7
CS Disable Time tCSD 50 ns 7
Data Setup Time tSU 5 ns 7
Data Hold Time tHD 10 ns 7
Serial Clock High Time tHI 20 ns 7
Serial Clock Low Time tLO 20 ns 7
Serial Clock Delay Time tCLD 50 ns 7
Serial Clock Enable Time tCLE 50 ns 7
Output Valid from SCK Low tDO 25 ns 7
Output Disable Time tDIS 25 ns Note 1 7
Reset Pulse Width (RESET) tMCLR 100 ns 7
Data Transfer Time to DR tDODR 25 ns Note 2 7
Operating Temperature Range TA -40 125 °C Note 1 7
Internal VREF Temperature Coefficient TCVREF 7 ppm/°C TA = -40°C to +125°C, VREFEXT = 0 5
Offset Error Drift 0.5 µV/°C 3
Gain Error Drift 1 ppm/°C 4
Integral Nonlinearity INL 5 ppm 4
Thermal Resistance, 20-Lead QFN θJA 43 °C/W 7

CAD (KiCad official)

  • Symbol: MCP3911A0-E
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20(4x4) (KiCad packages3D, STEP)
  • 3D model files: mcp3911a0-e-etched.step / mcp3911a0-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp3911a0-e.step / mcp3911a0-e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (74 pp, sha256 6aa4f0fb7c0af6d5, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF