DS90UB914ATRHSRQ1 from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDA	bidirectional	Data line for the bidirectional control bus (I2C-compatible, open drain) that requires an external pullup resistor to VDDIO.
2	SCL	bidirectional	Clock line for the bidirectional control bus (I2C-compatible, open drain) that requires an external pullup resistor to VDDIO.
3	VDDSSCG	power_in	SSCG PLL power supply, 1.8 V ±5%.
4	OSS_SEL	input	Output Sleep State select pin; sets the ROUT and PCLK output states when LOCK is low, as defined in Table 3.
5	OEN	input	Output enable input that controls the output states together with OSS_SEL, as defined in Table 3.
6	BISTEN	input	BIST enable pin; BISTEN = H enables BIST mode and BISTEN = L disables it.
7	VDDIO3	power_in	LVCMOS I/O buffer power, which can be connected to 1.8 V ±5% or 3.3 V ±10%.
8	PCLK	output	Pixel clock output whose strobe edge is set by the RRFB register; it becomes active before LOCK in 12-bit low-frequency and 10-bit modes and at the same time as LOCK in 12-bit high-frequency mode.
9	VSYNC	output	Vertical sync LVCMOS output that is restricted to no more than one transition per 10 PCLK cycles in 10-bit mode; leave open if unused.
10	HSYNC	output	Horizontal sync LVCMOS output that is restricted to no more than one transition per 10 PCLK cycles in 10-bit mode; leave open if unused.
11	ROUT[11]	output	Parallel LVCMOS data output that is active in 12-bit modes and inactive in 10-bit mode, where it should be left as No Connect.
12	ROUT[10]	output	Parallel LVCMOS data output that is active in 12-bit modes and inactive in 10-bit mode, where it should be left as No Connect.
13	ROUT[9]	output	Parallel LVCMOS data output that is active in both 10-bit and 12-bit modes; unused outputs should be No Connect.
14	ROUT[8]	output	Parallel LVCMOS data output that is active in both 10-bit and 12-bit modes; unused outputs should be No Connect.
15	ROUT[7]	output	Parallel LVCMOS data output that is active in both 10-bit and 12-bit modes; unused outputs should be No Connect.
16	ROUT[6]	output	Parallel LVCMOS data output that is active in both 10-bit and 12-bit modes; unused outputs should be No Connect.
17	VDDD	power_in	Digital core power supply, 1.8 V ±5%.
18	ROUT[5]	output	Parallel LVCMOS data output that is active in both 10-bit and 12-bit modes; unused outputs should be No Connect.
19	ROUT[4]	output	Parallel LVCMOS data output that is active in both 10-bit and 12-bit modes; unused outputs should be No Connect.
20	VDDIO2	power_in	LVCMOS I/O buffer power, which can be connected to 1.8 V ±5% or 3.3 V ±10%.
21	ROUT[3]	output	Parallel LVCMOS data output that is active in both 10-bit and 12-bit modes; unused outputs should be No Connect.
22	ROUT[2]	output	Parallel LVCMOS data output that is active in both 10-bit and 12-bit modes; unused outputs should be No Connect.
23	ROUT[1]	output	Parallel LVCMOS data output that is active in both 10-bit and 12-bit modes; unused outputs should be No Connect.
24	ROUT[0]	output	Parallel LVCMOS data output that is active in both 10-bit and 12-bit modes; unused outputs should be No Connect.
25	GPIO[3]	bidirectional	LVCMOS general-purpose I/O that can be an input for a serializer GPO or an output following local register settings, and should be left open if unused.
26	GPIO[2]	bidirectional	LVCMOS general-purpose I/O that can be an input for a serializer GPO or an output following local register settings, and should be left open if unused.
27	GPIO[1]	bidirectional	LVCMOS general-purpose I/O that can be used to control and respond to commands, and should be left open if unused.
28	GPIO[0]	bidirectional	LVCMOS general-purpose I/O that can be used to control and respond to commands, and should be left open if unused.
29	VDDIO1	power_in	LVCMOS I/O buffer power, which can be connected to 1.8 V ±5% or 3.3 V ±10%.
30	PDB	input	Power-down pin; PDB = H enables the deserializer, while PDB = L powers it down and resets programmed control register data to default values.
31	VDDCML1	power_in	CML and bidirectional control channel drive power, 1.8 V ±5%.
32	RIN1+	bidirectional	Noninverting CML differential input for the bidirectional control channel that must be AC-coupled with a 0.1 µF capacitor, or left open if unused.
33	RIN1-	bidirectional	Inverting CML differential input for the bidirectional control channel that must be AC-coupled with a 0.1 µF capacitor, or left open if unused; single-ended coax use requires a 0.047 µF AC-coupling capacitor in series with a 50 Ω resistor.
34	IDx[1]	input	Device ID address select that sets the I2C slave address, using a resistor to ground and a 10 kΩ pullup to the 1.8 V rail.
35	IDx[0]	input	Device ID address select that sets the I2C slave address, using a resistor to ground and a 10 kΩ pullup to the 1.8 V rail.
36	VDDR	power_in	Rx analog power supply, 1.8 V ±5%.
37	MODE	input	Analog device mode select that sets 12-bit low-frequency, 12-bit high-frequency, or 10-bit operation via a resistor to ground and a 10 kΩ pullup to the 1.8 V rail (VDD, not VDDIO).
38	CMLOUTP	output	CML loop-through output, to be routed to a test point or left open if unused.
39	CMLOUTN	output	CML loop-through output, to be routed to a test point or left open if unused.
40	VDDCML0	power_in	CML and bidirectional control channel drive power, 1.8 V ±5%.
41	RIN0+	bidirectional	Noninverting CML differential input for the FPD-Link III and bidirectional control channel that must be AC-coupled with a 0.1 µF capacitor, or left open if unused.
42	RIN0-	bidirectional	Inverting CML differential input for the FPD-Link III and bidirectional control channel that must be AC-coupled with a 0.1 µF capacitor, or left open if unused; single-ended coax use requires a 0.047 µF AC-coupling capacitor in series with a 50 Ω resistor.
43	RES	passive	Reserved pin that must always be tied low.
44	RES	passive	Reserved pin that must always be tied low.
45	VDDPLL	power_in	PLL power supply, 1.8 V ±5%.
46	SEL	input	MUX select line: SEL = L selects the RIN0± input (input A) and SEL = H selects the RIN1± input (input B).
47	PASS	output	BIST pass output that is H for error-free transmission and L when one or more errors are detected in the payload; leave open if unused.
48	LOCK	output	PLL lock status output that is H when locked and outputs are active, and L when unlocked, in which case ROUT and PCLK follow OSS_SEL; it may be used as a link status.
49	DAP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-48-EP(7x7)
Category	Interface ICs
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage, VDD_n (1.8 V)		-0.3		2.5	V		9
Supply voltage, VDDIO		-0.3		4	V		9
LVCMOS input voltage		-0.3			V	max printed as VDDIO + 0.3	9
CML receiver I/O voltage (VDD)		-0.3			V	max printed as VDD + 0.3	9
Junction temperature				150	°C		9
Storage temperature	Tstg	-65		150	°C		9
Supply Voltage (VDD_n)	VDD_n	1.71	1.8	1.89	V		9
LVCMOS Supply Voltage (VDDIO = 1.8 V)	VDDIO	1.71	1.8	1.89	V	VDDIO = 1.8 V	9
LVCMOS Supply Voltage (VDDIO = 3.3 V)	VDDIO	3	3.3	3.6	V	VDDIO = 3.3 V	9
Supply Noise VDD_n (1.8 V)				25	mVp-p	VDD_n (1.8 V); printed value placed in max column, verify	9
Supply Noise VDDIO (1.8 V)				25	mVp-p	VDDIO (1.8 V); printed value placed in max column, verify	9
Supply Noise VDDIO (3.3 V)				50	mVp-p	VDDIO (3.3 V); printed value placed in max column, verify	9
Power-Over-Coax Supply Noise				10	mVp-p	f = 30 Hz - 1 kHz, trise > 100 µs; measured differentially between DOUT+ and DOUT-; coax mode only	9
Operating Free Air Temperature (TA)	TA	-40	25	105	°C		9
PCLK Clock Frequency		25		100	MHz		9
Junction-to-ambient thermal resistance	RθJA		29.7		°C/W	RHS (WQFN) 48 pins	10
Junction-to-case (top) thermal resistance	RθJC(top)		10.9		°C/W	RHS (WQFN) 48 pins	10
Junction-to-board thermal resistance	RθJB		6.7		°C/W	RHS (WQFN) 48 pins	10
Junction-to-top characterization parameter	ψJT		0.1		°C/W	RHS (WQFN) 48 pins	10
Junction-to-board characterization parameter	ψJB		6.7		°C/W	RHS (WQFN) 48 pins	10
Junction-to-case (bottom) thermal resistance	RθJC(bot)		2.3		°C/W	RHS (WQFN) 48 pins	10
High Level Input Voltage (3.3 V I/O)	VIH	2			V	VIN = 3 V to 3.6 V; max printed as VIN, not recorded	10
Low Level Input Voltage (3.3 V I/O)	VIL			0.8	V	VIN = 3 V to 3.6 V	10
Input Current (3.3 V I/O)	IIN	-20		20	µA	VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V	10
High Level Output Voltage (3.3 V I/O)	VOH	2.4			V	VDDIO = 3 V to 3.6 V, IOH = −4 mA; max printed as VDDIO, not recorded	10
Low Level Output Voltage (3.3 V I/O)	VOL			0.4	V	VDDIO = 3 V to 3.6 V, IOL = 4 mA	10
Output Short Circuit Current, GPO outputs (3.3 V)	IOS	-15			mA	VOUT = 0 V; single printed value placed in min column, verify	10
Output Short Circuit Current, LVCMOS outputs (3.3 V)	IOS	-35			mA	VOUT = 0 V; single printed value placed in min column, verify	10
TRI-STATE Output Current, LVCMOS and GPO outputs (3.3 V)	IOZ	-20		20	µA	PDB = 0 V, VOUT = 0 V or VDD	10
Input Current (1.8 V I/O)	IIN	-20		20	µA	VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V	10
Low Level Output Voltage (1.8 V I/O)	VOL			0.45	V	VDDIO = 1.71 V to 1.89 V, IOL = 4 mA	10
Output Short Circuit Current, GPO outputs (1.8 V)	IOS	-11			mA	VOUT = 0 V; single printed value placed in min column, verify	10
Output Short Circuit Current, LVCMOS outputs (1.8 V)	IOS	-17			mA	VOUT = 0 V; single printed value placed in min column, verify	10
TRI-STATE Output Current, LVCMOS and GPO outputs (1.8 V)	IOZ	-20		20	µA	PDB = 0 V, VOUT = 0 V or VDD	10
CML Receiver Input Current	IIN	-20	1	20	µA	VIN = VDD or 0 V, VDD = 1.89 V	11
Differential Internal Termination Resistance	RT	80	100	120	Ω	Differential across RIN+ and RIN-	11
Single-ended Termination Resistance	RT	40	50	60	Ω	RIN+ or RIN-	11
Differential Input Voltage	VID	210			mV	Back Channel Disabled, (Figure 4); single printed value placed in min column, verify	11
Single-Ended Input Voltage	VIN	105			mV	Back Channel Disabled, (Figure 4); single printed value placed in min column, verify	11
Back Channel Frequency	ƒBC	3.3		4.2	MHz	two printed values assumed min and max, verify	11
Back Channel Differential Output Voltage	VOD-BC	350		540	mV	two printed values assumed min and max, verify	11
Back Channel Single-Ended Output Voltage	VOUT-BC	182		270	mV	two printed values assumed min and max, verify	11
Differential Output Eye Opening	Ew	0.45			UI	RL = 100 Ω, Jitter Frequency > f/15 (Figure 9)	11
Differential Output Eye Height	EH	200			mV		11
Deserializer (Rx) Total Supply Current, IDDIOR	IDDIOR		22	42	mA	VDDIO = 1.89 V, CL = 8 pF, worst case pattern, f = 100 MHz, 10-bit mode	12
Deserializer (Rx) Total Supply Current, IDDIOR	IDDIOR		19	39	mA	VDDIO = 1.89 V, CL = 8 pF, worst case pattern, f = 75 MHz, 12-bit high freq mode	12
Deserializer (Rx) Total Supply Current, IDDIOR	IDDIOR		16	32	mA	VDDIO = 1.89 V, CL = 8 pF, worst case pattern, f = 50 MHz, 12-bit low freq mode	12
Deserializer (Rx) Total Supply Current, IDDIOR	IDDIOR		42	55	mA	VDDIO = 3.6 V, CL = 8 pF, worst case pattern, f = 100 MHz, 10-bit mode	12
Deserializer (Rx) Total Supply Current, IDDIOR	IDDIOR		37	50	mA	VDDIO = 3.6 V, CL = 8 pF, worst case pattern, f = 75 MHz, 12-bit high freq mode	12
Deserializer (Rx) Total Supply Current, IDDIOR	IDDIOR		25	38	mA	VDDIO = 3.6 V, CL = 8 pF, worst case pattern, f = 50 MHz, 12-bit low freq mode	12
Deserializer (Rx) Supply Current, IDDR	IDDR		64	110	mA	VDD_n = 1.89 V, CL = 4 pF, worst case pattern, f = 100 MHz, 10-bit mode	13
Deserializer (Rx) Supply Current, IDDR	IDDR		67	114	mA	VDD_n = 1.89 V, CL = 4 pF, worst case pattern, f = 75 MHz, 12-bit high freq mode	13
Deserializer (Rx) Supply Current, IDDR	IDDR		63	96	mA	VDD_n = 1.89 V, CL = 4 pF, worst case pattern, f = 50 MHz, 12-bit low freq mode	13
Deserializer (Rx) Supply Current Power Down, IDDRZ	IDDRZ		42	900	µA	PDB = 0 V, all other LVCMOS inputs = 0 V, VDDIO = 1.89 V, default registers	13
Deserializer (Rx) VDDIO Supply Current Power Down, IDDIORZ	IDDIORZ		8	40	µA	PDB = 0 V, all other LVCMOS inputs = 0 V, VDDIO = 1.89 V	13
Deserializer (Rx) VDDIO Supply Current Power Down, IDDIORZ	IDDIORZ		360	800	µA	PDB = 0 V, all other LVCMOS inputs = 0 V, VDDIO = 3.6 V	13
LVCMOS Low-to-High Transition Time (PCLK)	tCLH	1.3	2	2.8	ns	VDDIO 1.71 V to 1.89 V or 3 V to 3.6 V, CL = 8 pF (lumped load), default registers	15
LVCMOS Low-to-High Transition Time (ROUT[11:0], HS, VS)	tDLH	1	2.5	4	ns	VDDIO 1.71 V to 1.89 V or 3 V to 3.6 V, CL = 8 pF (lumped load), default registers	15

CAD (KiCad official)

Symbol: DS90UB914ATRHSRQ1
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: ds90ub914atrhsrq1-etched.step / ds90ub914atrhsrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub914atrhsrq1.step / ds90ub914atrhsrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (69 pp, sha256 d4b97b56a1a2bbaf, retrieved 2026-10-30, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DS90UB914ATRHSRQ1

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3D Model

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