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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ATM90E32AS-AU-R

Microchip Tech · Energy Metering · TQFP-48(7x7)

ATM90E32AS-AU-R from Microchip Tech, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDD	power_in	Analog power supply (3.3V); should be connected to DVDD and decoupled with a 0.1μF capacitor.
2	AGND	power_in	Analog ground; provides reference for analog signal processing circuits.
3	I1P	input	Positive input to differential ADC channel 1 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain.
4	I1N	input	Negative input to differential ADC channel 1 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain.
5	I2P	input	Positive input to differential ADC channel 2 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain.
6	I2N	input	Negative input to differential ADC channel 2 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain.
7	I3P	input	Positive input to differential ADC channel 3 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain.
8	I3N	input	Negative input to differential ADC channel 3 for current sampling; accepts signals from 120μV to 720mV at 1x PGA gain.
9	IC	passive	Internal test/substrate connection; must always be connected to DGND in system applications.
10	IC	passive	Internal test/substrate connection; must always be connected to DGND in system applications.
11	Vref	power_in	Reference voltage output (1.2V nominal) for on-chip reference circuit; should be decoupled with 4.7μF and 0.1μF capacitors.
12	AGND	power_in	Analog ground; provides reference for analog signal processing circuits.
13	V1P	input	Positive input to differential ADC channel for voltage sampling of phase 1; accepts signals from 120μV to 720mV at 1x PGA gain.
14	V1N	input	Negative input to differential ADC channel for voltage sampling of phase 1; accepts signals from 120μV to 720mV at 1x PGA gain.
15	V2P	input	Positive input to differential ADC channel for voltage sampling of phase 2; accepts signals from 120μV to 720mV at 1x PGA gain.
16	V2N	input	Negative input to differential ADC channel for voltage sampling of phase 2; accepts signals from 120μV to 720mV at 1x PGA gain.
17	V3P	input	Positive input to differential ADC channel for voltage sampling of phase 3; accepts signals from 120μV to 720mV at 1x PGA gain.
18	V3N	input	Negative input to differential ADC channel for voltage sampling of phase 3; accepts signals from 120μV to 720mV at 1x PGA gain.
19	DGND	power_in	Digital ground; provides power return for digital circuitry.
20	OSCI	input	Crystal oscillator input or external clock source; accepts 16.384 MHz clock with ±20 ppm accuracy and 10pF-20pF load capacitance.
21	OSCO	output	Crystal oscillator output; connected to 16.384 MHz external crystal between OSCI and OSCO pins.
22	ZX0	output	Zero-crossing detection output (configurable source and type); outputs digital pulse when configured voltage or current signal crosses zero threshold.
23	ZX1	output	Zero-crossing detection output (configurable source and type); outputs digital pulse when configured voltage or current signal crosses zero threshold.
24	ZX2	output	Zero-crossing detection output (configurable source and type); outputs digital pulse when configured voltage or current signal crosses zero threshold.
25	CF1	output	All-phase-sum total active energy pulse output; generates pulse with 80ms width when period ≥160ms, or T/2 width for 10ms-160ms period.
26	CF2	output	All-phase-sum total reactive or apparent energy pulse output (configurable via CF2varh bit); generates pulse with 80ms width when period ≥160ms, or T/2 width for 10ms-160ms period.
27	CF3	output	All-phase-sum total active fundamental energy pulse output; generates pulse with 80ms width when period ≥160ms, or T/2 width for 10ms-160ms period.
28	CF4	output	All-phase-sum total active harmonic energy pulse output; generates pulse with 80ms width when period ≥160ms, or T/2 width for 10ms-160ms period.
29	WarnOut	output	Fatal error warning output (LVTTL); asserted high when metering-related parameter CRC checksum error is detected, otherwise stays low.
30	IRQ0	output	Interrupt output 0 (LVTTL); asserted when interrupt events in EMMIntState0 register occur, or when current detector output activated in Detection mode.
31	IRQ1	output	Interrupt output 1 (LVTTL); asserted when interrupt events in EMMIntState1 register occur, or when all three phase currents exceed detector threshold in Detection mode.
32	TEST	input	Test pin (LVTTL input); must always be connected to DGND in system applications.
33	PM0	input	Power mode configuration input (LSB); together with PM1 defines power mode (Idle=00, Detection=01, Partial Measurement=10, Normal=11).
34	PM1	input	Power mode configuration input (MSB); together with PM0 defines power mode (Idle=00, Detection=01, Partial Measurement=10, Normal=11).
35	NC	unconnected	No connection; should be left open (not connected) in system design.
36	IC	passive	Internal test/substrate connection; must always be connected to DGND in system applications.
37	CS	input	SPI chip select input (active low, LVTTL); must transition high-to-low for each SPI transaction and remain low for entire operation.
38	SCLK	input	SPI serial clock input (LVTTL); provides clock for SPI slave mode data transfer at 400-1100 kbps.
39	SDO	output	SPI serial data output (LVTTL); outputs 16-bit register data on falling edge of SCLK during SPI read operation.
40	SDI	input	SPI serial data input (LVTTL); accepts 16-bit instruction and data on rising edge of SCLK during SPI read/write operation.
41	RESET	input	Active-low reset input (LVTTL); resets chip registers and state when asserted, should connect through 0.1μF capacitor and 10kΩ resistor to VDD.
42	VDD18	power_out	1.8V regulated digital power supply output from on-chip regulator; must be connected together with pin 43 and bypassed with 10μF capacitor.
43	VDD18	power_out	1.8V regulated digital power supply output from on-chip regulator; must be connected together with pin 42 and bypassed with 10μF capacitor.
44	DGND	power_in	Digital ground; provides power return for digital circuitry.
45	NC	unconnected	No connection; should be left open (not connected) in system design.
46	NC	unconnected	No connection; should be left open (not connected) in system design.
47	DGND	power_in	Digital ground; provides power return for digital circuitry.
48	DVDD	power_in	Digital power supply (3.3V); should be decoupled with 10μF and 0.1μF capacitors.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	TQFP-48(7x7)
Category	Data Acquisition
Pins	48

CAD (KiCad official)

Symbol: ATM90E32AS-AU-R
Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: atm90e32as-au-r-etched.step / atm90e32as-au-r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atm90e32as-au-r.step / atm90e32as-au-r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (84 pp, sha256 f8ce8aacae3378c5, retrieved 2026-09-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF