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CY7C64215-56LTXCT

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy7c64215-56ltxctfactory-2.0.0extractor-text

Verified CY7C64215-56LTXCT

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 57 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY7C64215-56LTXCT · QFN-56-EP(8x8) · 57 pins
  • ✓copper: 57 copper pads, none touching another net
  • ✓datasheet: all 57 pin names found in the 46-page datasheet
  • ✓distributor: lcsc C2953062, digikey 448-CY7C64215-56LTXCTTR-ND, mouser 727-CY7C6421556LTXCT
  • ✓family: QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-7cwltk7q/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 57 pins = 57 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 57 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy7c64215-56ltxct.kicad_sym✓ cy7c64215-56ltxct.kicad_mod✓ cy7c64215-56ltxct.step
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3D Model

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Symbol & Footprint

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Contents

README

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CY7C64215-56LTXCT

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-56-EP(8x8)

CY7C64215-56LTXCT from Cypress Semicon, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2[3] bidirectional Digital I/O port pin that is also an analog mux input and a direct switched capacitor block input.
2 P2[1] bidirectional Digital I/O port pin that is also an analog mux input and a direct switched capacitor block input.
3 P4[7] bidirectional Digital I/O port pin with analog mux input capability.
4 P4[5] bidirectional Digital I/O port pin with analog mux input capability.
5 P4[3] bidirectional Digital I/O port pin with analog mux input capability.
6 P4[1] bidirectional Digital I/O port pin with analog mux input capability.
7 P3[7] bidirectional Digital I/O port pin with analog mux input capability.
8 P3[5] bidirectional Digital I/O port pin with analog mux input capability.
9 P3[3] bidirectional Digital I/O port pin with analog mux input capability.
10 P3[1] bidirectional Digital I/O port pin with analog mux input capability.
11 P5[7] bidirectional Digital I/O port pin with analog mux input capability.
12 P5[5] bidirectional Digital I/O port pin with analog mux input capability.
13 P5[3] bidirectional Digital I/O port pin with analog mux input capability.
14 P5[1] bidirectional Digital I/O port pin with analog mux input capability.
15 P1[7] bidirectional Digital I/O port pin with analog mux input capability, also the I2C serial clock (SCL).
16 P1[5] bidirectional Digital I/O port pin with analog mux input capability, also the I2C serial data (SDA).
17 P1[3] bidirectional Digital I/O port pin with analog mux input capability.
18 P1[1] bidirectional Digital I/O port pin with analog mux input capability, also I2C SCL and ISSP-SCLK.
19 VSS power_in Ground connection.
20 D+ bidirectional USB D+ data line.
21 D- bidirectional USB D- data line.
22 VDD power_in Supply voltage.
23 P7[7] bidirectional Digital I/O port pin.
24 P7[0] bidirectional Digital I/O port pin.
25 P1[0] bidirectional Digital I/O port pin with analog mux input capability, also I2C SDA and ISSP-SDATA.
26 P1[2] bidirectional Digital I/O port pin with analog mux input capability.
27 P1[4] bidirectional Digital I/O port pin with analog mux input capability, also the optional external clock input EXTCLK.
28 P1[6] bidirectional Digital I/O port pin with analog mux input capability.
29 P5[0] bidirectional Digital I/O port pin with analog mux input capability.
30 P5[2] bidirectional Digital I/O port pin with analog mux input capability.
31 P5[4] bidirectional Digital I/O port pin with analog mux input capability.
32 P5[6] bidirectional Digital I/O port pin with analog mux input capability.
33 P3[0] bidirectional Digital I/O port pin with analog mux input capability.
34 P3[2] bidirectional Digital I/O port pin with analog mux input capability.
35 P3[4] bidirectional Digital I/O port pin with analog mux input capability.
36 P3[6] bidirectional Digital I/O port pin with analog mux input capability.
37 P4[0] bidirectional Digital I/O port pin with analog mux input capability.
38 P4[2] bidirectional Digital I/O port pin with analog mux input capability.
39 P4[4] bidirectional Digital I/O port pin with analog mux input capability.
40 P4[6] bidirectional Digital I/O port pin with analog mux input capability.
41 P2[0] bidirectional Digital I/O port pin that is also an analog mux input and a direct switched capacitor block input.
42 P2[2] bidirectional Digital I/O port pin that is also an analog mux input and a direct switched capacitor block input.
43 P2[4] bidirectional Digital I/O port pin with analog mux input capability, also the external analog ground (AGND) input.
44 P2[6] bidirectional Digital I/O port pin with analog mux input capability, also the external voltage reference (VREF) input.
45 P0[0] bidirectional Digital I/O port pin that is also an analog column mux input.
46 P0[2] bidirectional Digital I/O port pin that is also an analog column mux input and column output.
47 P0[4] bidirectional Digital I/O port pin that is also an analog column mux input and column output.
48 P0[6] bidirectional Digital I/O port pin that is also an analog column mux input.
49 VDD power_in Supply voltage.
50 VSS power_in Ground connection.
51 P0[7] bidirectional Digital I/O port pin that is also an analog column mux input.
52 P0[5] bidirectional Digital I/O port pin that is also an analog column mux input and column output.
53 P0[3] bidirectional Digital I/O port pin that is also an analog column mux input and column output.
54 P0[1] bidirectional Digital I/O port pin that is also an analog column mux input.
55 P2[7] bidirectional Digital I/O port pin with analog mux input capability.
56 P2[5] bidirectional Digital I/O port pin with analog mux input capability.
57 EP power_in Center pad that should be connected to ground (VSS) for best mechanical, thermal and electrical performance, or else left electrically floated.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-56-EP(8x8)
Category Single Chip Microcomputer/Microcontroller
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature TSTG -55 100 °C 14
Supply voltage on VDD relative to VSS VDD -0.5 6 V 14
Maximum current into any port pin IMIO -25 50 mA 14
Maximum current into any port pin configured as analog driver IMAIO -50 50 mA 14
Electrostatic discharge voltage ESD 2000 V Human body model ESD 14
Latch up current LU 200 mA 14
Ambient temperature with power applied TA 0 70 °C 14
Commercial ambient temperature TAC 0 70 °C 14
Junction temperature TJ -40 100 °C 14
Supply voltage VDD 3 5.25 V USB hardware not functional when VDD is between 3.5 V and 4.35 V 15
Supply current, IMO = 24 MHz (5 V) IDD5 14 27 mA VDD = 5.0 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, analog power = off 15
Supply current, IMO = 24 MHz (3.3 V) IDD3 8 14 mA VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, analog power = off 15
Sleep mode current with POR, LVD, sleep timer, WDT ISB 3 6.5 µA Internal slow speed oscillator, VDD = 3.3 V, 0 °C < TA < 55 °C, analog power = off 15
Sleep mode current at high temperature ISBH 4 25 µA Internal slow speed oscillator, VDD = 3.3 V, 55 °C < TA < 70 °C, analog power = off 15
Pull-up resistor RPU 4 5.6 8 kΩ 16
Pull-down resistor RPD 4 5.6 8 kΩ 16
Low output level VOL 0.75 V IOL = 25 mA, VDD = 4.75 to 5.25 V 16
High-level source current IOH 10 mA 16
Low-level sink current IOL 25 mA 16
Input low level VIL 0.8 V VDD = 3.15 to 5.25 16
Input high level VIH 2.1 V VDD = 3.15 to 5.25 16
Input hysteresis VH 60 mV 16
Input leakage (absolute value) IIL 1 nA Gross tested to 1 µA 16
Capacitive load on pins as input CIN 3.5 10 pF Temp = 25 °C 16
Capacitive load on pins as output COUT 3.5 10 pF Temp = 25 °C 16
USB differential input sensitivity VDI 0.2 V / (D+), (D-) / 16
USB differential input common mode range VCM 0.8 2.5 V 16
USB single-ended receiver threshold VSE 0.8 2 V 16
USB transceiver capacitance CIN 20 pF 16
High Z state data line leakage IIO -10 10 µA 0 V < VIN < 3.3 V 16
External USB series resistor REXT 23 25 Ω In series with each USB pin 16
Static output high, driven VUOH 2.8 3.6 V 15 kΩ ± 5% to ground, internal pull-up enabled 16
Static output high, idle VUOHI 2.7 3.6 V 15 kΩ ± 5% to ground, internal pull-up enabled 16
Static output low VUOL 0.3 V 15 kΩ ± 5% to ground, internal pull-up enabled 16
USB driver output impedance ZO 28 44 Ω Including REXT resistor 16
D+/D- crossover voltage VCRS 1.3 2 V 16
VDD for programming and erase VDDP 4.5 5 5.5 V 24
Supply voltage for flash write operation VDDIWRITE 3.15 5.25 V 24
Supply current during programming or verify IDDP 15 30 mA 24
Flash endurance (per block) FlashENPB 50000 cycles Erase/write cycles per block 24
Flash data retention FlashDR 10 Years 24
IMO frequency for 24 MHz (5 V) FIMO245V 23.04 24 24.96 MHz Trimmed for 5 V operation using factory trim values 25
IMO frequency for 24 MHz (3.3 V) FIMO243V 22.08 24 25.92 MHz Trimmed for 3.3 V operation using factory trim values 25
IMO frequency with USB frequency locking FIMOUSB 23.94 24 24.06 MHz USB frequency locking enabled and USB traffic present 25
ILO frequency F32K1 15 32 64 kHz 25
Time from end of POR to CPU executing code TPOWERUP 16 100 ms 25
Rise time, normal strong mode TRiseF 3 18 ns Cload = 50 pF, VDD = 4.5 to 5.25 V, 10%-90% 26
Fall time, normal strong mode TFallF 2 18 ns Cload = 50 pF, VDD = 4.5 to 5.25 V, 10%-90% 26
USB transition rise time TRFS 4 20 ns For 50-pF load 26
USB transition fall time TFSS 4 20 ns For 50-pF load 26
Rise/fall time matching TRFMFS 90 111 % For 50-pF load 26
Frequency of SCLK FSCLK 0 8 MHz 29
Thermal impedance, 56-pin QFN θJA 20 °C/W Center thermal pad soldered to PCB ground plane 33

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC The emulator consists of a base unit that connects to the PC 7

CAD (KiCad official)

  • Symbol: CY7C64215-56LTXCT
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: cy7c64215-56ltxct-etched.step / cy7c64215-56ltxct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c64215-56ltxct.step / cy7c64215-56ltxct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (46 pp, sha256 0b74c71e9480da7a, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF