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Contents

README

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XD74LS86

XINLUDA · Logic Gates · DIP-14

XD74LS86 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A; high-level input voltage min 2 V, low-level max 0.8 V.
2 1B input Gate 1 input B; high-level input voltage min 2 V, low-level max 0.8 V.
3 1Y output Gate 1 exclusive-OR output; IOL max 8 mA, IOH max -400 µA.
4 2A input Gate 2 input A; high-level input voltage min 2 V, low-level max 0.8 V.
5 2B input Gate 2 input B; high-level input voltage min 2 V, low-level max 0.8 V.
6 2Y output Gate 2 exclusive-OR output; IOL max 8 mA, IOH max -400 µA.
7 GND power_in Ground, the reference for all voltage values.
8 3Y output Gate 3 exclusive-OR output; IOL max 8 mA, IOH max -400 µA.
9 3A input Gate 3 input A; high-level input voltage min 2 V, low-level max 0.8 V.
10 3B input Gate 3 input B; high-level input voltage min 2 V, low-level max 0.8 V.
11 4Y output Gate 4 exclusive-OR output; IOL max 8 mA, IOH max -400 µA.
12 4A input Gate 4 input A; high-level input voltage min 2 V, low-level max 0.8 V.
13 4B input Gate 4 input B; high-level input voltage min 2 V, low-level max 0.8 V.
14 VCC power_in Supply voltage, 4.75 V to 5.25 V recommended (nominal 5 V), absolute max 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 7 V see Note 1 (voltages with respect to network ground terminal) 3
Storage temperature range Tstg -65 150 C 3
Supply voltage VCC 4.75 5 5.25 V 4
High-level output current IOH -400 μA 4
Low-level output current IOL 8 mA 4
Operating free-air temperature TA 0 70 C 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 4
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VLI=VIL max, IOH = −400μA, VIH = 2V 4
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIL = VIL max, VIH = 2V, IOL = 4 mA 4
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIL = VIL max, VIH = 2V, IOL = 8 mA 4
Input current at maximum input voltage II 0.2 mA VCC = MAX, VI = 7 V 4
High-level input current IIH 40 μA VCC = MAX, VI = 2.7 V 4
Low-level input current IIL -0.8 mA VCC = MAX, VI = 0.4 V 4
Short-circuit output current IOS -20 -100 mA VCC = MAX 4
Supply current ICC 6.1 10 mA VCC = MAX, See Note 2 4
Propagation delay low-to-high tPLH 12 23 ns VCC = 5 V, TA = 25 C; A or B input, other input low; CL=15 pF, RL=2kΩ 4
Propagation delay high-to-low tPHL 10 17 ns VCC = 5 V, TA = 25 C; A or B input, other input low; CL=15 pF, RL=2kΩ 4
Propagation delay low-to-high tPLH 20 30 ns VCC = 5 V, TA = 25 C; A or B input, other input high; CL=15 pF, RL=2kΩ 4
Propagation delay high-to-low tPHL 13 22 ns VCC = 5 V, TA = 25 C; A or B input, other input high; CL=15 pF, RL=2kΩ 4

CAD (KiCad official)

  • Symbol: XD74LS86
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: xd74ls86-etched.step / xd74ls86-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls86.step / xd74ls86.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (5 pp, sha256 021d99806368de24, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF