component
ADS124S08IRHBT
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADS124S08IRHBT
Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-32-EP(5x5)
ADS124S08IRHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AINCOM | input | Common analog input for single-ended differential measurements. |
| 2 | AIN5 | input | Analog input 5 to the multiplexer. |
| 3 | AIN4 | input | Analog input 4 to the multiplexer. |
| 4 | AIN3 | input | Analog input 3 to the multiplexer. |
| 5 | AIN2 | input | Analog input 2 to the multiplexer. |
| 6 | AIN1 | input | Analog input 1 to the multiplexer. |
| 7 | AIN0 | input | Analog input 0 to the multiplexer. |
| 8 | START/SYNC | input | Digital input for conversion start and external synchronization; rising edge initiates a new conversion. |
| 9 | CS | input | Chip select input (active low); enables the SPI serial interface for communication. |
| 10 | DIN | input | Serial data input for SPI commands and register configuration data; latched on falling SCLK edge. |
| 11 | SCLK | input | Serial clock input for SPI interface; data is latched on the falling edge. |
| 12 | DOUT/DRDY | tri_state | Serial data output combined with data ready indicator (active low); tri-state output when CS is high. |
| 13 | DRDY | output | Data ready output (active low); indicates when new conversion data are available for retrieval. |
| 14 | DGND | power_in | Digital ground reference for all digital logic circuits. |
| 15 | IOVDD | power_in | Digital I/O power supply (2.7V to 3.6V); requires 100-nF or larger bypass capacitor to DGND. |
| 16 | DVDD | power_in | Digital core power supply (2.7V to 3.6V); requires 100-nF or larger bypass capacitor to DGND. |
| 17 | CLK | input | External clock input or internal oscillator selection; connect to DGND to use internal 4.096-MHz oscillator. |
| 18 | RESET | input | Active-low reset input; device initialization triggered when pulled low. |
| 19 | GPIO3/AIN11 | bidirectional | General-purpose I/O (programmable as input or output) or analog input 11 (ADS124S08 only). |
| 20 | GPIO2/AIN10 | bidirectional | General-purpose I/O (programmable as input or output) or analog input 10 (ADS124S08 only). |
| 21 | GPIO1/AIN9 | bidirectional | General-purpose I/O (programmable as input or output) or analog input 9 (ADS124S08 only). |
| 22 | GPIO0/AIN8 | bidirectional | General-purpose I/O (programmable as input or output) or analog input 8 (ADS124S08 only). |
| 23 | REFOUT | output | Positive voltage reference output (2.5V nominal); requires 1-µF to 47-µF capacitor to REFCOM if internal reference is enabled. |
| 24 | REFCOM | power_in | Negative voltage reference output; connect to AVSS. |
| 25 | NC | unconnected | No connection; leave unconnected or connect to AVSS. |
| 26 | AVDD | power_in | Positive analog power supply (2.7V to 5.25V single-ended or ±2.5V dual-rail); requires 330-nF or larger bypass capacitor to AVSS. |
| 27 | AVSS | power_in | Negative analog power supply and ground reference for all analog circuits. |
| 28 | AVSS-SW | power_in | Analog ground with integrated low-side switch for power management; connect to AVSS. |
| 29 | REFN0 | input | Negative external reference input 0 for alternative reference configuration. |
| 30 | REFP0 | input | Positive external reference input 0 for alternative reference configuration. |
| 31 | REFN1/AIN7 | input | Negative external reference input 1 or analog input 7 (ADS124S08 only) for flexible reference or measurement configuration. |
| 32 | REFP1/AIN6 | input | Positive external reference input 1 or analog input 6 (ADS124S08 only) for flexible reference or measurement configuration. |
| 33 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | ADC/DAC/Data Conversion |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
ADS124S08IRHBT - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
ads124s08irhbt-etched.step/ads124s08irhbt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads124s08irhbt.step/ads124s08irhbt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (115 pp, sha256
62eb7595c22ca2ef, retrieved 2026-10-03, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).