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74HC594T16-13

Diodes Incorporated · Shifting Register · TSSOP-16

74HC594T16-13 from Diodes Incorporated, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 output Parallel data output bit 1 from the 8-bit storage register. Push-pull CMOS output rated ±35mA continuous. Updated on the rising edge of STCP; asynchronously cleared to LOW when STR is asserted low.
2 Q2 output Parallel data output bit 2 from the 8-bit storage register. Push-pull CMOS output rated ±35mA continuous. Updated on the rising edge of STCP; cleared to LOW by STR.
3 Q3 output Parallel data output bit 3 from the 8-bit storage register. Push-pull CMOS output rated ±35mA continuous. Updated on the rising edge of STCP; cleared to LOW by STR.
4 Q4 output Parallel data output bit 4 from the 8-bit storage register. Push-pull CMOS output rated ±35mA continuous. Updated on the rising edge of STCP; cleared to LOW by STR.
5 Q5 output Parallel data output bit 5 from the 8-bit storage register. Push-pull CMOS output rated ±35mA continuous. Updated on the rising edge of STCP; cleared to LOW by STR.
6 Q6 output Parallel data output bit 6 from the 8-bit storage register. Push-pull CMOS output rated ±35mA continuous. Updated on the rising edge of STCP; cleared to LOW by STR.
7 Q7 output Parallel data output bit 7 (MSB) from the 8-bit storage register. Push-pull CMOS output rated ±35mA continuous. Updated on the rising edge of STCP; cleared to LOW by STR.
8 GND power_in Ground reference (0V). Continuous current through GND rated -70mA max.
9 Q7S output Serial data output from the last stage of the shift register, used for cascading multiple 74HC594 devices. Drive strength is lower than Qn outputs (±25mA max, 4mA at VCC=4.5V). Connects to the DS input of the next device in the chain.
10 SHR input Shift register reset, active LOW. Asynchronously clears all shift register stages to zero, independent of clocks. Schmitt-trigger input, accepts up to 6.0V.
11 SHCP input Shift register clock input. Serial data on DS is captured into shift register stage 0 on the rising edge; other stages shift toward Q7S. Schmitt-trigger input; fmax ~30 MHz at VCC=4.5V.
12 STCP input Storage register clock input. Rising edge transfers the contents of the shift register into the 8-bit output storage register, updating Q0-Q7. Schmitt-trigger input.
13 STR input Storage register reset, active LOW. Asynchronously clears all storage register (output) stages to LOW, independent of clocks. Schmitt-trigger input.
14 DS input Serial data input. Value present on DS is captured into shift register stage 0 on the rising edge of SHCP when SHR is HIGH. Schmitt-trigger input, accepts up to 6.0V regardless of VCC.
15 Q0 output Parallel data output bit 0 (LSB) from the 8-bit storage register. Push-pull CMOS output rated ±35mA continuous. Updated on the rising edge of STCP; cleared to LOW by STR.
16 VCC power_in Positive supply voltage, 2.0V to 6.0V recommended (absolute max +7.0V). Continuous supply current rated 70mA max. Bypass with 100nF ceramic near the pin.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package TSSOP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74HC594T16-13
  • 74HC594T16-13S16-13

CAD (KiCad official)

  • Symbol: 74HC594T16-13
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (10 pp, sha256 5361e09fd1f40a4b, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF