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TPS26632RGET
Public Made by Adomby adom
Texas Instruments Surge Protection Devices (SPDs), VQFN-24(4x4). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownTPS26632RGET
Texas Instruments · Surge Protection Devices (SPDs) · VQFN-24(4x4)
TPS26632RGET from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Power input, connects to the DRAIN of the internal FET. |
| 2 | IN | power_in | Power input, connects to the DRAIN of the internal FET. |
| 3 | B_GATE | output | Blocking FET gate driver output; connect to GATE of external NFET or leave floating if external FET is not used. |
| 4 | DRV | output | Blocking FET fast pulldown switch drive output; connect to GATE of external pulldown switch or leave floating if not used. |
| 5 | IN_SYS | power_in | Power input and supply voltage of the device; when using external Blocking FET connect to FET source, otherwise short to IN. |
| 6 | UVLO | input | Input for setting the programmable undervoltage lockout threshold; connect to GND to select internal default threshold. |
| 7 | PLIM | input | Input for setting the programmable output power limiting threshold; connect resistor to GND to set power limit or connect directly to GND to disable. |
| 8 | GND | power_in | Connect GND to system ground. |
| 9 | dVdT | bidirectional | Input/output; capacitor from this pin to GND sets output voltage slew rate for inrush current control. |
| 10 | ILIM | bidirectional | Input/output; resistor from this pin to GND sets the overload and short-circuit current limit. |
| 11 | MODE | input | Mode selection pin for overload fault response; open for latch-off, shorted to GND for auto-retry. |
| 12 | SHDN | input | Shutdown pin; pull below 0.8 V to enter shutdown mode, pull above 2 V to enable device. |
| 13 | IMON | output | Analog current monitor output sourcing scaled current proportional to internal FET current; connect resistor to GND to convert to voltage. |
| 14 | FLT | output | Fault event indicator, open-drain output asserts active-low under undervoltage, overvoltage, overload, or thermal shutdown. |
| 15 | PGTH | input | PGOOD comparator input; threshold voltage determines power-good indication. |
| 16 | PGOOD | output | Active-high power-good output; indicates when PGTH has crossed the rising threshold and internal FET is enhanced. |
| 17 | OUT | power_out | Power output of the device; source for protected load. |
| 18 | OUT | power_out | Power output of the device; parallel connection for increased current capability. |
| 19 | N.C | unconnected | No connect. |
| 20 | N.C | unconnected | No connect. |
| 21 | N.C | unconnected | No connect. |
| 22 | N.C | unconnected | No connect. |
| 23 | N.C | unconnected | No connect. |
| 24 | PowerPAD | power_in | PowerPAD™ integrated circuit package thermal ground connection; connect to GND plane for heat sinking but do not use as only electrical GND connection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24(4x4) |
| Category | Circuit Protection |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage IN_SYS | -60 | 67 | V | 5 | |||
| Input voltage IN_SYS (10 ms transient) | -60 | 75 | V | 10 ms transient, TA = 25 ℃ | 5 | ||
| Voltage IN, OUT, UVLO, FLT, PGOOD, PGTH | -0.3 | 67 | V | 5 | |||
| Voltage IN (10 ms transient) | -0.3 | 75 | V | 10 ms transient, TA = 25 ℃ | 5 | ||
| IN_SYS, OUT (10 ms transient) | -85 | V | 10 ms transient, with a blocking FET | 5 | |||
| BGATE voltage | -60 | 81 | V | 5 | |||
| BGATE, IN_SYS voltage | -0.3 | 14 | V | 5 | |||
| DRV voltage | -60 | 72 | V | 5 | |||
| DRV, IN_SYS voltage | -0.3 | 20 | V | 5 | |||
| Voltage OVP, dVdT, IMON, MODE, SHDN, ILIM, PLIM | -0.3 | 5.5 | V | 5 | |||
| Sink current IFLT, IdVdT, IPGOOD | IFLT, IdVdT, IPGOOD | 10 | mA | 5 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| Input voltage | IN_SYS, IN | 4.5 | 60 | V | 5 | ||
| Voltage OUT, UVLO, PGTH, PGOOD, FLT | 0 | 60 | V | 5 | |||
| Voltage OVP, dVdT, IMON, MODE | 0 | 4 | V | 5 | |||
| Voltage SHDN | 0 | 5 | V | 5 | |||
| ILIM resistance | 3 | 30 | kΩ | 5 | |||
| PLIM resistance | 60.4 | 150 | kΩ | 5 | |||
| Operating junction temperature | TJ | -40 | 25 | 125 | °C | 6 | |
| Operating input voltage | V(IN_SYS) | 4.5 | 60 | V | 6 | ||
| Supply current, enabled | IQ(ON) | 1.38 | 1.7 | mA | Enabled: V(SHDN) = 2 V | 6 | |
| Supply current, shutdown | IQ(OFF) | 21 | 60 | µA | V(SHDN) = 0 V | 6 | |
| Ground current during reverse polarity | I(GND) | 144 | 200 | µA | V(IN_SYS) = -24V, V(IN) = Floating, V(OUT) = 0 V | 6 | |
| Over voltage clamp | V(OVC) | 32 | 32.8 | 35 | V | TPS26632 and TPS26633, V(IN_SYS) > 35 V, I(OUT) = 1 mA | 6 |
| Factory set V(IN_SYS) undervoltage trip level, rising | V(INSYS_UVLO) | 15.1 | 15.46 | 15.9 | V | V(IN_SYS) rising, V(UVLO) = 0 V | 6 |
| Factory set V(IN_SYS) undervoltage trip level, falling | V(INSYS_UVLO) | 14 | 14.47 | 15.1 | V | V(IN_SYS) falling, V(UVLO) = 0 V | 6 |
| UVLO threshold voltage, rising | V(UVLOR) | 1.176 | 1.2 | 1.224 | V | 6 | |
| UVLO threshold voltage, falling | V(UVLOF) | 1.09 | 1.122 | 1.15 | V | 6 | |
| UVLO input leakage current | I(UVLO) | -150 | 8 | 150 | nA | 0 V ≤ V(UVLO) ≤ 60 V | 6 |
| Over load current limit | I(OL) | 0.54 | 0.6 | 0.66 | A | R(ILIM) = 30 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Over load current limit | I(OL) | 1.84 | 2 | 2.16 | A | R(ILIM) = 9 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Over load current limit | I(OL) | 4.185 | 4.5 | 4.815 | A | R(ILIM) = 4.02 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Over load current limit | I(OL) | 5.58 | 6 | 6.42 | A | R(ILIM) = 3 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Max output power | P(PLIM) | 94 | 100 | 106 | W | R(PLIM) = 100 kΩ | 7 |
| Max output power | P(PLIM) | 141.9 | 151 | 160.1 | W | R(PLIM) = 150 kΩ | 7 |
| B_GATE clamp voltage | V(B_GATE) | 8.3 | 10.23 | 14 | V | V(B_GATE), V(IN_SYS) | 7 |
| Blocking FET gate drive current | I(B_GATE) | 16 | 19.4 | 23 | µA | V(B_GATE), V(IN_SYS) = 1 V | 7 |
| B_GATE pull down resistance | Rpd_BGATE | 800 | 1010 | 1200 | kΩ | 7 | |
| DRV logic high level | V(DRV_OH) | 3 | 4.25 | 5.2 | V | V(DRV), V(IN_SYS), C(DRV) ≤ 50 pF | 7 |
| IN to OUT total ON resistance | RON | 26 | 30.44 | 34.5 | mΩ | 0.6 A ≤ I(OUT) ≤ 6 A, TJ = 25°C | 7 |
| IN to OUT total ON resistance | RON | 33 | 45 | mΩ | 0.6 A ≤ I(OUT) ≤ 6 A, TJ = 85°C | 7 | |
| IN to OUT total ON resistance | RON | 19 | 30.44 | 53 | mΩ | 0.6 A ≤ I(OUT) ≤ 6 A, -40°C ≤ TJ ≤ +125°C | 7 |
| V(IN_SYS), V(OUT) threshold for reverse protection comparator, rising | V(REVTH) | -20 | -15 | -9 | mV | 7 | |
| V(IN_SYS), V(OUT) threshold for reverse protection comparator, falling | V(FWDTH) | 45 | 57 | 67 | mV | 7 | |
| dVdT charging current | I(dVdT) | 1.775 | 2 | 2.225 | µA | V(dVdT) = 0 V | 7 |
| dVdT to OUT gain | GAIN(dVdT) | 23.5 | 25 | 26 | V/V | V(OUT)/V(dVdT) | 7 |
| dVdT maximum capacitor voltage | V(dVdTmax) | 3.8 | 4.17 | 4.75 | V | 7 | |
| dVdT discharging resistance | R(dVdT) | 10 | 16.6 | 26.6 | Ω | 7 | |
| Open circuit voltage | V(SHDN) | 2.48 | 2.7 | 3.3 | V | I(SHDN) = 0.1 µA | 7 |
| Short circuit protect current | I(SCP) | 45 | A | 7 | |||
| SHDN threshold voltage for low IQ shutdown, falling | V(SHUTF) | 0.8 | V | 7 | |||
| OUT leakage during input supply brownout | Ilkg(OUT) | -100 | µA | V(IN_SYS) = 0 V, V(OUT) = 24 V, V(IN) = Floating, V(SHDN) = 2V, Sinking | 7 | ||
| IMON resistance | 1 | kΩ | 5 | ||||
| External capacitance IN, IN_SYS, OUT | 0.1 | µF | 5 | ||||
| dVdT external capacitance | 10 | nF | 5 | ||||
| Junction-to-ambient thermal resistance | RθJA | 31.4 | °C/W | RGE (VSON), 24 pins | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 23.2 | °C/W | RGE (VSON), 24 pins | 6 | ||
| Junction-to-board thermal resistance | RθJB | 10.2 | °C/W | RGE (VSON), 24 pins | 6 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 2.8 | °C/W | RGE (VSON), 24 pins | 6 |
CAD (KiCad official)
- Symbol:
TPS26632RGET - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
tps26632rget-etched.step/tps26632rget-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps26632rget.step/tps26632rget.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (60 pp, sha256
63ce6e9453e4499b, retrieved 2026-10-21, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).