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CD4060DA.TB

Public Made by Adom

by adom

Wuxi I-core Elec Counters / Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD4060DA.TB

Wuxi I-core Elec · Counters / Dividers · DIP-16

CD4060DA.TB from Wuxi I-core Elec, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q11 output Buffered counter output Q11, forced LOW while MR is HIGH.
2 Q12 output Buffered counter output Q12, forced LOW while MR is HIGH.
3 Q13 output Buffered counter output Q13, forced LOW while MR is HIGH.
4 Q5 output Buffered counter output Q5, forced LOW while MR is HIGH.
5 Q4 output Buffered counter output Q4, forced LOW while MR is HIGH.
6 Q6 output Buffered counter output Q6, forced LOW while MR is HIGH.
7 Q3 output Buffered counter output Q3, forced LOW while MR is HIGH.
8 VSS power_in Ground reference (0 V); all voltages in the datasheet are referenced to VSS.
9 CEXT passive External capacitor connection for the oscillator (CX), with CX max values given in the AC characteristics table.
10 REXT passive Oscillator pin for the external timing resistor (RX); RC oscillator use is not recommended below 7 V for RX below 50 kΩ.
11 RS input Clock input and oscillator pin; the counter advances on the negative-going transition of RS, with maximum external clock frequency of 3.5 MHz at 5 V, 8 MHz at 10 V and 12 MHz at 15 V.
12 MR input Master reset; a HIGH level resets the counter (Q3 to Q9 and Q11 to Q13 LOW) independent of other input conditions.
13 Q8 output Buffered counter output Q8, forced LOW while MR is HIGH.
14 Q7 output Buffered counter output Q7, forced LOW while MR is HIGH.
15 Q9 output Buffered counter output Q9, forced LOW while MR is HIGH.
16 VDD power_in Supply voltage, recommended range 3 V to 15 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Wuxi I-core Elec
Package DIP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage (absolute maximum) VDD -0.5 18 V voltages referenced to VSS 6
DC input current IIK -10 10 mA any one input 6
input voltage VI -0.5 V all inputs; printed max is VDD+0.5 6
storage temperature Tstg -65 150 ℃ 6
total power dissipation Ptot 500 mW 6
device dissipation per output transistor P 100 mW per output transistor 6
soldering temperature TL 245 ℃ 10s, DIP 6
supply voltage (recommended) VDD 3 15 V 6
ambient temperature Tamb -40 85 ℃ in free air 6
input pulse width tw 100 ns f=100kHz; VDD=5V 6
input pulse width tw 40 ns f=100kHz; VDD=10V 6
input pulse width tw 30 ns f=100kHz; VDD=15V 6
reset pulse width twR 120 ns VDD=5V 6
reset pulse width twR 60 ns VDD=10V 6
reset pulse width twR 40 ns VDD=15V 6
input pulse frequency fRS fRS 3.5 MHz external pulse source; VDD=5V 6
input pulse frequency fRS fRS 8 MHz external pulse source; VDD=10V 6
input pulse frequency fRS fRS 12 MHz external pulse source; VDD=15V 6
supply current IDD 0.04 5 uA Tamb=25℃; VIN=0V, VDD=5V 7
supply current IDD 0.04 10 uA Tamb=25℃; VIN=0V, VDD=10V 7
supply current IDD 0.04 20 uA Tamb=25℃; VIN=0V, VDD=15V 7
LOW-level output current IOL 0.51 1 mA Tamb=25℃; VO=0.4V, VDD=5V 7
LOW-level output current IOL 1.3 2.6 mA Tamb=25℃; VO=0.5V, VDD=10V 7
LOW-level output current IOL 3.4 6.8 mA Tamb=25℃; VO=1.5V, VDD=15V 7
HIGH-level output current IOH -0.51 -1 mA Tamb=25℃; VO=4.6V, VDD=5V 7
HIGH-level output current IOH -1.6 -3.2 mA Tamb=25℃; VO=2.5V, VDD=5V 7
HIGH-level output current IOH -1.3 -2.6 mA Tamb=25℃; VO=9.5V, VDD=10V 7
HIGH-level output current IOH -3.4 -6.8 mA Tamb=25℃; VO=13.5V, VDD=15V 7
LOW-level output voltage VOL 0 0.05 V Tamb=25℃; VDD=5V 7
HIGH-level output voltage VOH 4.95 5 V Tamb=25℃; VDD=5V 7
HIGH-level output voltage VOH 9.95 10 V Tamb=25℃; VDD=10V 7
HIGH-level output voltage VOH 14.95 15 V Tamb=25℃; VDD=15V 7
LOW-level input voltage VIL 1.5 V Tamb=25℃; VDD=5V 7
LOW-level input voltage VIL 3 V Tamb=25℃; VDD=10V 7
LOW-level input voltage VIL 4 V Tamb=25℃; VDD=15V 7
HIGH-level input voltage VIH 3.5 V Tamb=25℃; VDD=5V 7
HIGH-level input voltage VIH 7 V Tamb=25℃; VDD=10V 7
HIGH-level input voltage VIH 11 V Tamb=25℃; VDD=15V 7
input leakage current II -0.1 0.1 uA Tamb=25℃; VIN=0V, VDD=15V 7
supply current IDD 5 uA Tamb=-40℃; VIN=0V, VDD=5V 7
supply current IDD 10 uA Tamb=-40℃; VIN=0V, VDD=10V 7
supply current IDD 20 uA Tamb=-40℃; VIN=0V, VDD=15V 7
supply current IDD 150 uA Tamb=+85℃; VIN=0V, VDD=5V 7
supply current IDD 300 uA Tamb=+85℃; VIN=0V, VDD=10V 7
supply current IDD 600 uA Tamb=+85℃; VIN=0V, VDD=15V 7
maximum clock frequency fmax 3.5 7 MHz input RS; VDD=5V 8
maximum clock frequency fmax 8 16 MHz input RS; VDD=10V 8
maximum clock frequency fmax 12 24 MHz input RS; VDD=15V 8
propagation delay time tPHL, tPLH 370 740 ns RS to Q3 out; VDD=5V 8
propagation delay time tPHL, tPLH 150 300 ns RS to Q3 out; VDD=10V 8
propagation delay time tPHL, tPLH 100 200 ns RS to Q3 out; VDD=15V 8
input capacitance CI 5 7.5 pF any input 8
maximum oscillator frequency 530 650 810 kHz CX=15pF, RS=30kΩ, RX=15kΩ; VDD=10V 9
maximum oscillator frequency 690 800 940 kHz CX=15pF, RS=30kΩ, RX=15kΩ; VDD=15V 9
propagation delay time tPHL, tPLH 50 100 ns Qn to Qn+1; VDD=10V 8
propagation delay time tPHL, tPLH 40 80 ns Qn to Qn+1; VDD=15V 8

CAD (KiCad official)

  • Symbol: CD4060DA.TB
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4060da-tb-etched.step / cd4060da-tb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4060da-tb.step / cd4060da-tb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I-core Elec datasheet (14 pp, sha256 9da10c692685b29e, retrieved 2026-10-29, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF