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SN74AHC125DBR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, SSOP-14-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74AHC125DBR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SSOP-14-208mil
SN74AHC125DBR from Texas Instruments, in a SSOP-14-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable for gate 1; active-low control that enables buffer when low, forcing output to high-impedance when high. |
| 2 | 1A | input | Data input to gate 1; logic level passed to output 1Y when output enable 1OE is low. |
| 3 | 1Y | tri_state | Data output from gate 1; reflects input 1A when 1OE is low, high-impedance when 1OE is high. |
| 4 | 2OE | input | Output enable for gate 2; active-low control that enables buffer when low, forcing output to high-impedance when high. |
| 5 | 2A | input | Data input to gate 2; logic level passed to output 2Y when output enable 2OE is low. |
| 6 | 2Y | tri_state | Data output from gate 2; reflects input 2A when 2OE is low, high-impedance when 2OE is high. |
| 7 | GND | power_in | Ground; negative supply reference. |
| 8 | 3Y | tri_state | Data output from gate 3; reflects input 3A when 3OE is low, high-impedance when 3OE is high. |
| 9 | 3A | input | Data input to gate 3; logic level passed to output 3Y when output enable 3OE is low. |
| 10 | 3OE | input | Output enable for gate 3; active-low control that enables buffer when low, forcing output to high-impedance when high. |
| 11 | 4Y | tri_state | Data output from gate 4; reflects input 4A when 4OE is low, high-impedance when 4OE is high. |
| 12 | 4A | input | Data input to gate 4; logic level passed to output 4Y when output enable 4OE is low. |
| 13 | 4OE | input | Output enable for gate 4; active-low control that enables buffer when low, forcing output to high-impedance when high. |
| 14 | VCC | power_in | Positive supply voltage; 2 V to 5.5 V per Section 5.3 recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-14-208mil |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74AHC125DBR - Footprint:
Package_SO:SSOP-14_5.3x6.2mm_P0.65mm - 3D model: SSOP-14-208mil (KiCad packages3D, STEP)
- 3D model files:
sn74ahc125dbr-etched.step/sn74ahc125dbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ahc125dbr.step/sn74ahc125dbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (46 pp, sha256
b79e065712962829, retrieved 2026-09-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).