component
TPIC6A595DWR
Public Made by Adomby adom
Texas Instruments Shifting Register, SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTPIC6A595DWR
Texas Instruments · Shifting Register · SOIC-24-300mil
TPIC6A595DWR from Texas Instruments, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DRAIN2 | passive | Open-drain DMOS output 2 with 50 V switching capability and 350 mA continuous sink current. |
| 2 | DRAIN3 | passive | Open-drain DMOS output 3 with 50 V switching capability and 350 mA continuous sink current. |
| 3 | SRCLR | input | Shift register clear, active low; a low level clears all registers in the device. |
| 4 | G | input | Output enable, active low; when high all drain outputs are turned off, and it can be used for global PWM dimming. |
| 5 | PGND | power_in | Power ground, internally connected to other PGND pins and must be externally connected to the power system ground. |
| 6 | PGND | power_in | Power ground, internally connected to other PGND pins and must be externally connected to the power system ground. |
| 7 | PGND | power_in | Power ground, internally connected to other PGND pins and must be externally connected to the power system ground. |
| 8 | PGND | power_in | Power ground, internally connected to other PGND pins and must be externally connected to the power system ground. |
| 9 | RCK | input | Register clock; data transfers from shift register to storage register on its rising edge, and read/write data is valid only when RCK is low. |
| 10 | SRCK | input | Shift register clock; serial data is shifted in on its rising edge. |
| 11 | DRAIN4 | passive | Open-drain DMOS output 4 with 50 V switching capability and 350 mA continuous sink current. |
| 12 | DRAIN5 | passive | Open-drain DMOS output 5 with 50 V switching capability and 350 mA continuous sink current. |
| 13 | DRAIN6 | passive | Open-drain DMOS output 6 with 50 V switching capability and 350 mA continuous sink current. |
| 14 | DRAIN7 | passive | Open-drain DMOS output 7 with 50 V switching capability and 350 mA continuous sink current. |
| 15 | SEROUT | output | Serial data output for cascading to the SER IN of the next device. |
| 16 | LGND | power_in | Logic ground, to be connected externally at a single point to PGND. |
| 17 | PGND | power_in | Power ground, internally connected to other PGND pins and must be externally connected to the power system ground. |
| 18 | PGND | power_in | Power ground, internally connected to other PGND pins and must be externally connected to the power system ground. |
| 19 | PGND | power_in | Power ground, internally connected to other PGND pins and must be externally connected to the power system ground. |
| 20 | PGND | power_in | Power ground, internally connected to other PGND pins and must be externally connected to the power system ground. |
| 21 | VCC | power_in | Logic supply voltage, recommended 4.5 V to 5.5 V and absolute maximum 7 V. |
| 22 | SERIN | input | Serial data input to the 8-bit shift register. |
| 23 | DRAIN0 | passive | Open-drain DMOS output 0 with 50 V switching capability and 350 mA continuous sink current. |
| 24 | DRAIN1 | passive | Open-drain DMOS output 1 with 50 V switching capability and 350 mA continuous sink current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-24-300mil |
| Category | Logic ICs |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source breakdown voltage | V(BR)DSX | 50 | V | ID = 1mA | 5 | ||
| Source-drain diode forward voltage | VSD | 0.8 | 1.1 | V | IF = 350mA | 5 | |
| Serial output low-level voltage | VOL | 0 | 0.1 | V | IOL = 20µA | 5 | |
| Serial output low-level voltage | VOL | 0.2 | 0.5 | V | IOL = 4mA | 5 | |
| High-level input current | IIH | 1 | µA | VI = VCC | 5 | ||
| Low-level input current | IIL | -1 | µA | VI = 0 | 5 | ||
| Output current at start of chopping | IO(chop) | 0.6 | 0.8 | 1.1 | A | TC = 25°C | 5 |
| Logic supply current | ICC | 0.5 | 5 | mA | IO = 0, VI = VCC or 0 | 5 | |
| Logic supply current at frequency | ICC(FRQ) | 1.3 | mA | fSRCK = 5MHz, VI = VCC or 0, IO = 0, VCC = 5V, CL = 30pF | 5 | ||
| Nominal current | I(nom) | 350 | mA | VDS(on) = 0.5V, VCC = 5V, I(nom) = ID, TC = 85°C | 5 | ||
| Off-state drain current | ID | 0.1 | 1 | µA | VDS = 40V, TC = 25°C | 5 | |
| Off-state drain current | ID | 0.2 | 5 | µA | VDS = 40V, TC = 125°C | 5 | |
| Static drain-source on-state resistance | rDS(on) | 1 | 1.5 | Ω | ID = 350mA, TC = 25°C | 5 | |
| Static drain-source on-state resistance | rDS(on) | 1.7 | 2.5 | Ω | ID = 350mA, TC = 125°C | 5 | |
| Logic supply voltage | VCC | 7 | V | 4 | |||
| Logic input voltage range | VI | -0.3 | 7 | V | 4 | ||
| Power DMOS drain-source voltage | VDS | 50 | V | 4 | |||
| Source-drain diode continuous anode current | 1 | A | 4 | ||||
| Source-drain diode pulsed anode current | 2 | A | pulse ≤100µs, duty ≤2% | 4 | |||
| Pulsed drain current per output, all outputs on | IDN | 1.1 | A | TA = 25°C, pulse ≤100µs, duty ≤2% | 4 | ||
| Peak drain current, single output | 1.1 | A | TA = 25°C, pulse ≤100µs, duty ≤2% | 4 | |||
| Single-pulse avalanche energy | EAS | 75 | mJ | 4 | |||
| Avalanche current | IAS | 600 | mA | drain supply 15V, TJS = 25°C, L = 210mH | 4 | ||
| Operating case temperature range | TC | -40 | 125 | °C | 4 | ||
| Operating virtual junction temperature range | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Lead temperature | 260 | °C | 1.6mm from case for 10 seconds | 4 | |||
| Logic supply voltage | VCC | 4.5 | 5.5 | V | 4 | ||
| Pulsed drain output current | -1.8 | 0.6 | A | TC = 25°C, VCC = 5V, pulse ≤100µs, duty ≤2% | 4 | ||
| Setup time, SER IN high before SRCK rise | tsu | 10 | ns | 4 | |||
| Hold time, SER IN high before SRCK rise | th | 10 | ns | 4 | |||
| Pulse duration | tw | 20 | ns | 4 | |||
| Operating case temperature | TC | -40 | 125 | °C | 4 | ||
| Power rating, DW package | 1750 | mW | TC ≤ 25°C | 4 | |||
| Power rating, DW package | 350 | mW | TC = 125°C | 4 | |||
| Junction-to-case thermal resistance, DW | RθJC | 10 | °C/W | equal power in all 8 outputs | 6 | ||
| Junction-to-ambient thermal resistance, DW | RθJA | 50 | °C/W | equal power in all 8 outputs | 6 |
CAD (KiCad official)
- Symbol:
TPIC6A595DWR - Footprint:
Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm - 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
- 3D model files:
tpic6a595dwr-etched.step/tpic6a595dwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpic6a595dwr.step/tpic6a595dwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
26ea17c96981700b, retrieved 2026-10-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).