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MSP430FR2000IRLLT
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), QFN-24-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR2000IRLLT
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFN-24-EP(3x3)
MSP430FR2000IRLLT from Texas Instruments, in a QFN-24-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TEST/SBWTCK | input | Test mode enable pin; Spy-Bi-Wire clock input for JTAG debug interface. |
| 2 | RST/NMI/SBWTDIO | bidirectional | Reset input (active low) with integrated hysteresis; configurable as external NMI or Spy-Bi-Wire data I/O. |
| 3 | DVCC | power_in | Digital core supply voltage; 1.8V to 3.6V with 4.7µF to 10µF bypass capacitor recommended (±20% tolerance or better). |
| 4 | DVSS | power_in | Ground reference for digital core supply. |
| 5 | P2.7/TB0CLK/XIN | bidirectional | General-purpose I/O P2.7; Timer B clock input (TBCLK) or 32kHz crystal oscillator input (XIN). |
| 6 | NC | unconnected | No internal connection; leave floating or connect to ground per application requirements. |
| 7 | P2.6/MCLK/XOUT | bidirectional | General-purpose I/O P2.6; Master Clock output (0-16MHz) or crystal oscillator output (XOUT). |
| 8 | P2.0/TB0.1/COUT | bidirectional | General-purpose I/O P2.0; Timer B capture/compare channel or enhanced comparator output (COUT). |
| 9 | NC | unconnected | No internal connection; leave floating or connect to ground per application requirements. |
| 10 | NC | unconnected | No internal connection; leave floating or connect to ground per application requirements. |
| 11 | P2.1/TB0.2 | bidirectional | General-purpose I/O P2.1; Timer B capture/compare channel (TB0.2). |
| 12 | NC | unconnected | No internal connection; leave floating or connect to ground per application requirements. |
| 13 | P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+ | bidirectional | General-purpose I/O P1.7; UART transmit data, SPI slave-in-master-out, Timer B output, JTAG test data output, or buffered 1.2V reference voltage output. |
| 14 | P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6 | bidirectional | General-purpose I/O P1.6; UART receive data, SPI slave-out-master-in, Timer B capture/compare, or JTAG test data input. |
| 15 | P1.5/UCA0CLK/TMS/A5 | bidirectional | General-purpose I/O P1.5; SPI clock output or JTAG test mode select input. |
| 16 | P1.4/UCA0STE/TCK/A4 | bidirectional | General-purpose I/O P1.4; SPI slave transmit enable or JTAG test clock input. |
| 17 | P1.3/UCA0TXD/UCA0SIMO/C3/A3 | bidirectional | General-purpose I/O P1.3; UART transmit data, SPI slave-in-master-out, or comparator input. |
| 18 | NC | unconnected | No internal connection; leave floating or connect to ground per application requirements. |
| 19 | P1.2/UCA0RXD/UCA0SOMI/TB0TRG/C2/A2/Veref- | bidirectional | General-purpose I/O P1.2; UART receive data, SPI slave-out-master-in, Timer B trigger, comparator input, or ADC negative reference input. |
| 20 | P1.0/UCA0STE/SMCLK/C0/A0/Veref+ | bidirectional | General-purpose I/O P1.0; SPI slave transmit enable, Sub-Master Clock output, comparator input, or ADC positive reference input. |
| 21 | NC | unconnected | No internal connection; leave floating or connect to ground per application requirements. |
| 22 | NC | unconnected | No internal connection; leave floating or connect to ground per application requirements. |
| 23 | P1.1/UCA0CLK/ACLK/C1/A1 | bidirectional | General-purpose I/O P1.1; Auxiliary Clock output (up to 40kHz), SPI clock, or comparator input. |
| 24 | NC | unconnected | No internal connection; leave floating or connect to ground per application requirements. |
| 25 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-24-EP(3x3) |
| Category | Embedded Processors & Controllers |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
MSP430FR2000IRLLT - Footprint:
Package_DFN_QFN:QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm - 3D model: QFN-24-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
msp430fr2000irllt-etched.step/msp430fr2000irllt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2000irllt.step/msp430fr2000irllt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (87 pp, sha256
7505f67fee2c23fa, retrieved 2026-09-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).