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SN74HCS595PWR
Public Made by Adomby adom
Texas Instruments Shifting Register, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HCS595PWR
Texas Instruments · Shifting Register · TSSOP-16
SN74HCS595PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | output | QB parallel 3-state output of the storage register. |
| 2 | QC | output | QC parallel 3-state output of the storage register. |
| 3 | QD | output | QD parallel 3-state output of the storage register. |
| 4 | QE | output | QE parallel 3-state output of the storage register. |
| 5 | QF | output | QF parallel 3-state output of the storage register. |
| 6 | QG | output | QG parallel 3-state output of the storage register. |
| 7 | QH | output | QH parallel 3-state output of the storage register. |
| 8 | GND | power_in | Ground. |
| 9 | QH' | output | Serial output of the shift register, can be used for cascading. |
| 10 | SRCLR | input | Shift register clear, active low, with Schmitt-trigger input. |
| 11 | SRCLK | input | Shift register clock, rising edge triggered. |
| 12 | RCLK | input | Output (storage) register clock, rising edge triggered. |
| 13 | OE | input | Output enable, active low; when high the storage register outputs are high-impedance. |
| 14 | SER | input | Serial data input. |
| 15 | QA | output | QA parallel 3-state output of the storage register. |
| 16 | VCC | power_in | Positive supply, 2 V to 6 V recommended operating range (absolute max 7 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Continuous output current | IO | -35 | 35 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -70 | 70 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | Guaranteed by design | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -4000 | 4000 | V | Human-body model, ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD CDM | V(ESD) | -1500 | 1500 | V | Charged-device model, JESD22-C101 | 4 | |
| Supply voltage | VCC | 2 | 5 | 6 | V | 4 | |
| Input voltage | VI | 0 | 6 | V | 0 to VCC | 4 | |
| Output voltage | VO | 0 | 6 | V | 0 to VCC | 4 | |
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 141.2 | °C/W | PW (TSSOP) 16 pins | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 78.8 | °C/W | PW (TSSOP) 16 pins | 4 | ||
| Junction-to-board thermal resistance | RθJB | 85.8 | °C/W | PW (TSSOP) 16 pins | 4 | ||
| Junction-to-top characterization parameter | ΨJT | 27.7 | °C/W | PW (TSSOP) 16 pins | 4 | ||
| Junction-to-board characterization parameter | ΨJB | 85.5 | °C/W | PW (TSSOP) 16 pins | 4 | ||
| Positive switching threshold | VT+ | 0.7 | 1.5 | V | VCC = 2 V | 5 | |
| Positive switching threshold | VT+ | 1.7 | 3.15 | V | VCC = 4.5 V | 5 | |
| Positive switching threshold | VT+ | 2.1 | 4.2 | V | VCC = 6 V | 5 | |
| Negative switching threshold | VT- | 0.3 | 1 | V | VCC = 2 V | 5 | |
| Negative switching threshold | VT- | 0.9 | 2.2 | V | VCC = 4.5 V | 5 | |
| Negative switching threshold | VT- | 1.2 | 3 | V | VCC = 6 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.2 | 1 | V | VCC = 2 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.4 | 1.4 | V | VCC = 4.5 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 | 1.6 | V | VCC = 6 V | 5 | |
| High-level output voltage | VOH | 4 | 4.3 | V | VI = VIH or VIL, IOH = -6 mA, VCC = 4.5 V | 5 | |
| High-level output voltage | VOH | 5.4 | 5.75 | V | VI = VIH or VIL, IOH = -7.8 mA, VCC = 6 V | 5 | |
| Low-level output voltage | VOL | 0.002 | 0.1 | V | VI = VIH or VIL, IOL = 20 µA, VCC = 2 V to 6 V | 5 | |
| Low-level output voltage | VOL | 0.18 | 0.3 | V | VI = VIH or VIL, IOL = 6 mA, VCC = 4.5 V | 5 | |
| Low-level output voltage | VOL | 0.22 | 0.33 | V | VI = VIH or VIL, IOL = 7.8 mA, VCC = 6 V | 5 | |
| Input leakage current | II | -1 | 0.1 | 1 | µA | VI = VCC or 0, VCC = 6 V | 5 |
| Off-state (high-impedance state) output current | IOZ | -5 | 0.5 | 5 | µA | VO = VCC or 0, VCC = 6 V | 5 |
| Supply current | ICC | 0.1 | 2 | µA | VI = VCC or 0, IO = 0, VCC = 6 V | 5 | |
| Input capacitance | Ci | 5 | pF | VCC = 2 V to 6 V | 5 | ||
| Power dissipation capacitance per gate | Cpd | 40 | pF | No load, VCC = 2 V to 6 V | 7 | ||
| Pulse duration SRCLK or RCLK high or low | tw | 9 | ns | VCC = 2 V, -40°C to 125°C, CL = 50 pF | 5 | ||
| Pulse duration SRCLK or RCLK high or low | tw | 7 | ns | VCC = 4.5 V, -40°C to 125°C, CL = 50 pF | 5 | ||
| Pulse duration SRCLR low | tw | 10 | ns | VCC = 2 V, -40°C to 125°C, CL = 50 pF | 5 | ||
| Pulse duration SRCLR low | tw | 7 | ns | VCC = 4.5 V, -40°C to 125°C, CL = 50 pF | 5 | ||
| Setup time SER before SRCLK↑ | tsu | 13 | ns | VCC = 2 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Setup time SER before SRCLK↑ | tsu | 5 | ns | VCC = 4.5 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Setup time SER before SRCLK↑ | tsu | 4 | ns | VCC = 6 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Max switching frequency | fmax | 19 | MHz | VCC = 2 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Max switching frequency | fmax | 60 | MHz | VCC = 4.5 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Max switching frequency | fmax | 75 | MHz | VCC = 6 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Propagation delay SRCLK to QH' | tpd | 28 | ns | VCC = 2 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Propagation delay SRCLK to QH' | tpd | 10 | ns | VCC = 4.5 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Propagation delay SRCLK to QH' | tpd | 9 | ns | VCC = 6 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Propagation delay RCLK to QA - QH | tpd | 37 | ns | VCC = 2 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Propagation delay RCLK to QA - QH | tpd | 12 | ns | VCC = 4.5 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Propagation delay RCLK to QA - QH | tpd | 10 | ns | VCC = 6 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Enable time OE to QA - QH | ten | 27 | ns | VCC = 2 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Enable time OE to QA - QH | ten | 13 | ns | VCC = 4.5 V, -40°C to 125°C, CL = 50 pF | 6 | ||
| Enable time OE to QA - QH | ten | 11 | ns | VCC = 6 V, -40°C to 125°C, CL = 50 pF | 6 |
CAD (KiCad official)
- Symbol:
SN74HCS595PWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hcs595pwr-etched.step/sn74hcs595pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hcs595pwr.step/sn74hcs595pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
04561b546ff9e2c0, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).