ISO7421ED from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC1	power_in	Power supply for side 1 (VCC1), recommended 3.0 V to 5.5 V with respect to GND1.
2	OUTA	output	Channel A output on side 1, rated for up to ±4 mA recommended output current.
3	INB	input	Channel B input on side 1, with high-level input voltage of 2 V to 5.5 V and low-level of 0 V to 0.8 V.
4	GND1	power_in	Ground connection for VCC1.
5	GND2	power_in	Ground connection for VCC2.
6	OUTB	output	Channel B output on side 2, rated for up to ±4 mA recommended output current.
7	INA	input	Channel A input on side 2, with high-level input voltage of 2 V to 5.5 V and low-level of 0 V to 0.8 V.
8	VCC2	power_in	Power supply for side 2 (VCC2), recommended 3.0 V to 5.5 V with respect to GND2.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Communication Interface Chip/UART/485/232
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	-0.5		6	V	VCC1, VCC2	5
Voltage at IN, OUT	VI	-0.5			V	max VCC + 0.5, must not exceed 6 V	5
Output current	IO	-15		15	mA		5
Maximum surge immunity	VSRG			4000	VPK	Supports IEC 61000-4-5	5
Maximum junction temperature	TJ(Max)			150	°C		5
Storage temperature	Tstg	-65		150	°C		5
ESD HBM	V(ESD)	-3000		3000	V	Human body model, ANSI/ESDA/JEDEC JS-001	5
ESD CDM	V(ESD)	-1500		1500	V	Charged-device model, JESD22-C101	5
ESD MM	V(ESD)	-200		200	V	Machine model, ANSI/ESDS5.2-1996	5
Supply voltage	VCC1, VCC2	3		5.5	V		5
High-level output current	IOH			-4	mA		5
Low-level output current	IOL			4	mA		5
High-level input voltage	VIH	2		5.5	V		5
Low-level input voltage	VIL	0		0.8	V		5
Input pulse duration	tui	20			ns		5
Signaling rate	1/tui	0		50	Mbps	Under typical conditions capable of > 150 Mbps	5
Junction temperature	TJ	-40		136	°C		5
Ambient temperature	TA	-40	25	125	°C		5
Junction-to-ambient thermal resistance, low-K board	RθJA		212		°C/W	D (SOIC) 8 pins, Low-K board	5
Junction-to-ambient thermal resistance, high-K board	RθJA		116.6		°C/W	D (SOIC) 8 pins, High-K board	5
Junction-to-case (top) thermal resistance	RθJC(top)		71.6		°C/W		5
Junction-to-board thermal resistance	RθJB		57.3		°C/W		5
Junction-to-top characterization parameter	ψJT		28.3		°C/W		5
Junction-to-board characterization parameter	ψJB		56.8		°C/W		5
Device power dissipation	PD			138	mW	VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty-cycle square wave	9
High-level output voltage	VOH		4.6		V	IOH = -4 mA; VCC1 and VCC2 = 5 V ± 10%; min is VCCO, 0.8	6
High-level output voltage	VOH		5		V	IOH = -20 μA; VCC1 and VCC2 = 5 V ± 10%; min is VCCO, 0.1	6
Low-level output voltage	VOL		0.2	0.4	V	IOL = 4 mA; VCC1 and VCC2 = 5 V ± 10%	6
Low-level output voltage	VOL		0	0.1	V	IOL = 20 μA; VCC1 and VCC2 = 5 V ± 10%	6
Input threshold voltage hysteresis	VI(HYS)		400		mV	VCC1 and VCC2 = 5 V ± 10%	6
High-level input current	IIH			10	μA	INx at 0 V or VCCI	6
Low-level input current	IIL	-10			μA	INx at 0 V or VCCI	6
Common-mode transient immunity	CMTI	25	50		kV/μs	VI = VCCI or 0 V; see Figure 18	6
Supply current ICC1, ISO7421x	ICC1		2.3	3.6	mA	DC to 1 Mbps, DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF; VCC1 and VCC2 = 5 V ± 10%	6
Supply current ICC2, ISO7421x	ICC2		2.3	3.6	mA	DC to 1 Mbps, DC Input: VI = VCCI or 0 V, AC Input: CL = 15 pF; VCC1 and VCC2 = 5 V ± 10%	6
Supply current ICC1, ISO7421x	ICC1		2.9	4.5	mA	10 Mbps, CL = 15 pF; VCC1 and VCC2 = 5 V ± 10%	6
Supply current ICC2, ISO7421x	ICC2		2.9	4.5	mA	10 Mbps, CL = 15 pF; VCC1 and VCC2 = 5 V ± 10%	6
Supply current ICC1, ISO7421x	ICC1		4.3	6	mA	25 Mbps, CL = 15 pF; VCC1 and VCC2 = 5 V ± 10%	6
Supply current ICC2, ISO7421x	ICC2		4.3	6	mA	25 Mbps, CL = 15 pF; VCC1 and VCC2 = 5 V ± 10%	6
Supply current ICC1, ISO7421x	ICC1		6	8.5	mA	50 Mbps, CL = 15 pF; VCC1 and VCC2 = 5 V ± 10%	6
Supply current ICC2, ISO7421x	ICC2		6	8.5	mA	50 Mbps, CL = 15 pF; VCC1 and VCC2 = 5 V ± 10%	6
Propagation delay time	tPLH, tPHL		7	11	ns	See Figure 16; VCC1 and VCC2 = 5 V ± 10%	10
Pulse width distortion, ISO7421x	PWD		0.3	3.7	ns	/tPHL, tPLH/; VCC1 and VCC2 = 5 V ± 10%	10
Channel-to-channel output skew time, ISO7421x	tsk(o)		0.3	2	ns	VCC1 and VCC2 = 5 V ± 10%	10
Part-to-part skew time, ISO7421x	tsk(pp)			4.9	ns	VCC1 and VCC2 = 5 V ± 10%	10
Output signal rise time	tr		1.8		ns	See Figure 16; VCC1 and VCC2 = 5 V ± 10%	10
Output signal fall time	tf		1.7		ns	See Figure 16; VCC1 and VCC2 = 5 V ± 10%	10
Fail-safe output delay time from input power loss	tfs		6		μs	See Figure 17; VCC1 and VCC2 = 5 V ± 10%	10
Propagation delay time, ISO7421x	tPLH, tPHL		8	13.5	ns	See Figure 16; VCC1 = 5 V ± 10%, VCC2 = 3.3 V ± 10%	10
Propagation delay time, ISO7421x	tPLH, tPHL		7.5	14	ns	See Figure 16; VCC1 = 3.3 V ± 10%, VCC2 = 5 V ± 10%	11
Propagation delay time	tPLH, tPHL		8.5	14	ns	See Figure 16; VCC1 and VCC2 = 3.3 V ± 10%	11
Maximum working isolation voltage	VIORM		566		VPEAK	DIN V VDE V 0884-10	18
Maximum transient isolation voltage	VIOTM		4242		VPEAK	VTEST = VIOTM = 4242 VPK, t = 60 sec (qualification), t = 1 sec (100% production)	18
Maximum withstand isolation voltage	VISO		2500		VRMS	UL 1577, VTEST = VISO = 2500 VRMS, t = 60 sec (qualification)	18
Barrier capacitance, input to output	CIO		1		pF	VIO = 0.4 sin (2πft), f = 1 MHz	17

CAD (KiCad official)

Symbol: ISO7421ED
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: iso7421ed-etched.step / iso7421ed-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); iso7421ed.step / iso7421ed.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (35 pp, sha256 947d3a765c7e0123, retrieved 2026-10-31, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ISO7421ED

Verified ISO7421ED

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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