component
A31010SEHALT-10
Public Made by Adomby adom
Allegro MicroSystems LLC Linear Hall Sensors, DFN-6(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownA31010SEHALT-10
Allegro MicroSystems LLC · Linear Hall Sensors · DFN-6(2x3)
A31010SEHALT-10 from Allegro MicroSystems LLC, in a DFN-6(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supply pin for the sensor, specified at 2.5 V to 3.5 V (3.0 V typical), with a 7 V absolute maximum supply voltage. |
| 2 | OUT | output | Unidirectional analog output that is proportional to the applied magnetic field; the output voltage must not exceed VCC + 0.1 V, and the output needs a resistive load of at least 15 kΩ and a capacitive load of at most 10 nF. |
| 3 | GND | power_in | Ground reference; all device ratings are referenced to this pin. |
| 4 | GND | power_in | Ground reference; all device ratings are referenced to this pin. |
| 5 | SLEEP | input | Active-low sleep control: pulling it below VSL (0.2 × VCC) enters sleep mode, driving it above VSH (0.45 × VCC) returns the device to active mode, and the input range is −0.1 V to VCC + 0.5 V. |
| 6 | VREF | power_in | Supply input for the ratiometric reference, which must be between 2.5 V and VCC, with a 7 V absolute maximum rating. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | DFN-6(2x3) |
| Category | Magnetic Sensors |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 2.5 | 3 | 3.5 | V | 3 | |
| Supply Current (Active Mode) | ICC | 3.2 | 3.6 | mA | Active Mode | 3 | |
| Supply Zener Clamp Voltage | VCCZ | 6 | 8.3 | V | ICC = 7 mA | 3 | |
| Output Capacitive Load | CL | 10 | nF | 3 | |||
| Output Resistive Load | RL | 15 | kΩ | 3 | |||
| Ratiometric Reference Voltage | VREF | 2.5 | V | 3 | |||
| Ratiometric Reference Zener Clamp Voltage | VREFZ | 6 | 8.3 | V | IVREF = 3 mA | 3 | |
| Ratiometric Reference Input Resistance | RREF | 200 | kΩ | VSLEEP > VSH, VCC = VCC(TYP) | 3 | ||
| SLEEP Input Voltage Range | VSLEEP | -0.1 | V | 3 | |||
| Power-On Time | tPO | 40 | 60 | µs | VCC > VCC(MIN), VSLEEP > VSH, VCC slew rate = 1 V/µs, CL ≤ 10 nF, RL ≥ 15 kΩ | 3 | |
| Optimized Sensing Range (A31010SEHALT-10) | BR | 0 | 250 | G | 4 | ||
| SLEEP Wakeup Time | tWU | 40 | 60 | µs | VSLEEP > VSH, VCC > VCC(MIN), CL ≤ 10 nF, RL ≥ 15 kΩ | 4 | |
| Supply Voltage | VCC | 7 | V | 2 | |||
| Reverse Supply Voltage | VRCC | -0.1 | V | 2 | |||
| Reference Voltage | VREF | 7 | V | 2 | |||
| Reverse Reference Voltage | VRREF | -0.1 | V | 2 | |||
| Logic Supply Voltage | VSLEEP | 32 | V | VCC > 2.5 V | 2 | ||
| Reverse Output Voltage | VROUT | -0.1 | V | 2 | |||
| Operating Ambient Temperature | TA | -20 | 85 | °C | 2 | ||
| Junction Temperature | TJ(MAX) | 165 | °C | 2 | |||
| Storage Temperature | Tstg | -65 | 170 | °C | 2 | ||
| Package Thermal Resistance (1-layer PCB) | RθJA | 221 | °C/W | 1-layer PCB with copper limited to solder pads | 8 | ||
| Package Thermal Resistance (2-layer PCB) | RθJA | 70 | °C/W | 2-layer PCB with 0.6 in.2 of copper area each side, connected by thermal vias | 8 | ||
| Package Thermal Resistance (4-layer PCB) | RθJA | 50 | °C/W | 4-layer PCB based on JEDEC standard | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | nominal height micro-leaded package (MLP/DFN). It is lead (Pb) free with 100% matte tin leadframe plating. | 1 |
CAD (KiCad official)
- Symbol:
A31010SEHALT-10 - Footprint:
Package_DFN_QFN:DFN-6-1EP_3x2mm_P0.5mm_EP1.65x1.35mm - 3D model: DFN-6(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
a31010sehalt-10-etched.step/a31010sehalt-10-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a31010sehalt-10.step/a31010sehalt-10.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (10 pp, sha256
dc11ef766db3da23, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).