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CA-IS3740LW
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCA-IS3740LW
Chipanalog · Digital Isolators · SOIC-16
CA-IS3740LW from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | A-side supply voltage, with a recommended operating range of 2.375 V to 5.5 V. |
| 2 | GNDA | power_in | A-side ground reference point. |
| 3 | VI1 | input | A-side logic input for channel 1, a Schmitt-trigger input with VIH of at least 2.0 V and VIL of at most 0.8 V. |
| 4 | VI2 | input | A-side logic input for channel 2, a Schmitt-trigger input with VIH of at least 2.0 V and VIL of at most 0.8 V. |
| 5 | VI3 | input | A-side logic input for channel 3 on the CA-IS3740 (the datasheet label is VI3/VO3, but VI3 is an input on this device), with VIH of at least 2.0 V and VIL of at most 0.8 V. |
| 6 | VI4 | input | A-side logic input for channel 4 on the CA-IS3740 (the datasheet label is VI4/VO4, but VI4 is an input on this device), with VIH of at least 2.0 V and VIL of at most 0.8 V. |
| 7 | NC | unconnected | No internal connection on the CA-IS3740; the pin may be left floating or tied to VDD or GND. |
| 8 | GNDA | power_in | A-side ground reference point. |
| 9 | GNDB | power_in | B-side ground reference point. |
| 10 | ENB | input | B-side output enable, internally pulled up to local VDD; a logic low puts outputs VO1 to VO4 into high impedance, and it should be tied to a defined logic level in noisy environments. |
| 11 | VO4 | output | B-side logic output for channel 4 on the CA-IS3740, with a typical output impedance of 50 Ω. |
| 12 | VO3 | output | B-side logic output for channel 3 on the CA-IS3740, with a typical output impedance of 50 Ω. |
| 13 | VO2 | output | B-side logic output for channel 2, with a typical output impedance of 50 Ω. |
| 14 | VO1 | output | B-side logic output for channel 1, with a typical output impedance of 50 Ω. |
| 15 | GNDB | power_in | B-side ground reference point. |
| 16 | VDDB | power_in | B-side supply voltage, with a recommended operating range of 2.375 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDA, VDDB | VDDA, VDDB | -0.5 | 7 | V | 5 | ||
| Input voltage Ax, Bx, ENx | Vin | -0.5 | V | 5 | |||
| Output current IO | IO | -20 | 20 | mA | 5 | ||
| Junction temperature TJ | TJ | 150 | °C | 5 | |||
| Storage temperature range TSTG | TSTG | -65 | 150 | °C | 5 | ||
| Supply voltage VDDA, VDDB | VDDA, VDDB | 2.375 | 5.5 | V | 5 | ||
| UVLO threshold on rising VDD | VDD(UVLO+) | 1.95 | 2.24 | 2.37 | V | 5 | |
| UVLO threshold on falling VDD | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | 5 | |
| UVLO hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | 5 | |
| High-level output current IOH | IOH | -4 | mA | VDDO = 5V | 5 | ||
| Low-level output current IOL | IOL | 4 | mA | VDDO = 5V | 5 | ||
| High-level output current IOH | IOH | -2 | mA | VDDO = 3.3V | 5 | ||
| Low-level output current IOL | IOL | 2 | mA | VDDO = 3.3V | 5 | ||
| High-level output current IOH | IOH | -1 | mA | VDDO = 2.5V | 5 | ||
| Low-level output current IOL | IOL | 1 | mA | VDDO = 2.5V | 5 | ||
| Input threshold logic high | VIH | 2 | V | 5 | |||
| Input threshold logic low | VIL | 0.8 | V | 5 | |||
| Signaling data rate | DR | 0 | 150 | Mbps | 5 | ||
| Ambient temperature TA | TA | -40 | 27 | 125 | °C | 5 | |
| Output logic-low voltage VOL | VOL | 0.2 | 0.4 | V | VDDA=VDDB=5V±10%, TA=-40 to 125°C; IOL = 4mA | 9 | |
| Input threshold logic high VIT+(IN) | VIT+(IN) | 2 | V | VDDA=VDDB=5V±10%, TA=-40 to 125°C | 9 | ||
| Input threshold logic low VIT-(IN) | VIT-(IN) | 0.8 | V | VDDA=VDDB=5V±10%, TA=-40 to 125°C | 9 | ||
| Input high-level leakage current IIH | IIH | 20 | µA | VDDA=VDDB=5V±10%, TA=-40 to 125°C; VIH = VDDA at Ax, Bx or ENx | 9 | ||
| Input low-level leakage current IIL | IIL | -20 | µA | VDDA=VDDB=5V±10%, TA=-40 to 125°C; VIL = 0 V at Ax, Bx or ENx | 9 | ||
| Common-mode transient immunity CMTI | CMTI | 100 | 150 | kV/µs | VDDA=VDDB=5V±10%, TA=-40 to 125°C; VI = VDDI1 or 0 V, VCM = 1200 V; Fig 8-4 | 9 | |
| Output impedance tolerance (typ 50 Ω) | ZO | -40 | 40 | % | Normal isolator channel output impedance, footnote 2 | 9 | |
| Supply current IDDA, enable-off, CA-IS3740L | IDDA | 1.3 | 2.1 | mA | VDDA=VDDB=5V±10%; ENB = 0 V; VIN = 0V (CA-IS3740L) | 10 | |
| Supply current IDDB, enable-off, CA-IS3740L | IDDB | 2.5 | 3.5 | mA | VDDA=VDDB=5V±10%; ENB = 0 V; VIN = 0V (CA-IS3740L) | 10 | |
| Supply current IDDA, DC signal, CA-IS3740L | IDDA | 1.3 | 2.1 | mA | VDDA=VDDB=5V±10%; ENB = VDDB; VIN = 0V (CA-IS3740L) | 10 | |
| Supply current IDDB, DC signal, CA-IS3740L | IDDB | 2.7 | 3.9 | mA | VDDA=VDDB=5V±10%; ENB = VDDB; VIN = 0V (CA-IS3740L) | 10 | |
| Supply current IDDA, AC 1 Mbps | IDDA | 3.9 | 5.8 | mA | VDDA=VDDB=5V±10%; ENB = VDDB; all inputs 50% duty 5V square wave; CL = 15 pF; 1Mbps (500kHz) | 10 | |
| Supply current IDDB, AC 1 Mbps | IDDB | 4.4 | 6.1 | mA | VDDA=VDDB=5V±10%; ENB = VDDB; all inputs 50% duty 5V square wave; CL = 15 pF; 1Mbps (500kHz) | 10 | |
| Supply current IDDA, AC 10 Mbps | IDDA | 3.9 | 5.8 | mA | VDDA=VDDB=5V±10%; ENB = VDDB; all inputs 50% duty 5V square wave; CL = 15 pF; 10Mbps (5MHz) | 10 | |
| Supply current IDDB, AC 10 Mbps | IDDB | 18.7 | 24.8 | mA | VDDA=VDDB=5V±10%; ENB = VDDB; all inputs 50% duty 5V square wave; CL = 15 pF; 10Mbps (5MHz) | 10 | |
| Supply current IDDA, AC 100 Mbps | IDDA | 4.7 | 6.8 | mA | VDDA=VDDB=5V±10%; ENB = VDDB; all inputs 50% duty 5V square wave; CL = 15 pF; 100Mbps (50MHz) | 10 | |
| Supply current IDDB, AC 100 Mbps | IDDB | 41 | 54.7 | mA | VDDA=VDDB=5V±10%; ENB = VDDB; all inputs 50% duty 5V square wave; CL = 15 pF; 100Mbps (50MHz) | 10 | |
| Propagation pulse width minimum PWmin | PWmin | 5 | ns | VDDA=VDDB=5V±10%, TA=-40 to 125°C | 13 | ||
| Propagation delay tPLH, tPHL | tPLH, tPHL | 5 | 12 | 16 | ns | VDDA=VDDB=5V±10%; Fig 8-1 | 13 |
| Pulse width distortion PWD | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/; VDDA=VDDB=5V±10% | 13 | |
| Channel-to-channel output skew tsk(o) | tsk(o) | 0.4 | 2.5 | ns | Same-direction channels; VDDA=VDDB=5V±10%; footnote 1 | 13 | |
| Part-to-part output skew tsk(pp) | tsk(pp) | 2 | 4.5 | ns | VDDA=VDDB=5V±10%; footnote 2 | 13 | |
| Output rise time tr | tr | 2.5 | 4 | ns | VDDA=VDDB=5V±10%; Fig 8-1 | 13 | |
| Output fall time tf | tf | 2.5 | 4 | ns | VDDA=VDDB=5V±10%; Fig 8-1 | 13 | |
| Disable propagation delay, output high to high-Z tPHZ | tPHZ | 8 | 13 | ns | VDDA=VDDB=5V±10%; Fig 8-2 | 13 | |
| Disable propagation delay, output low to high-Z tPLZ | tPLZ | 8 | 17 | ns | VDDA=VDDB=5V±10%; Fig 8-2 | 13 | |
| Enable propagation delay, high-Z to high tPZH (L variant) | tPZH | 10 | 20 | ns | CA-IS374xL; VDDA=VDDB=5V±10%; Fig 8-2 | 13 | |
| Enable propagation delay, high-Z to low tPZL (L variant) | tPZL | 10 | 25 | ns | CA-IS374xL; VDDA=VDDB=5V±10%; Fig 8-2 | 13 | |
| Default output delay from UVLO tDO | tDO | 8 | 12 | µs | VDDA=VDDB=5V±10%; Fig 8-3 | 13 | |
| Start-up time tSU | tSU | 15 | 40 | µs | VDDA=VDDB=5V±10% | 13 | |
| Output logic-high voltage VOH | VOH | 4.8 | V | VDDA=VDDB=5V±10%, TA=-40 to 125°C; IOH = -4mA; Fig 8-2 | 9 | ||
| Output logic-high voltage VOH | VOH | 3.1 | V | VDDA=VDDB=3.3V±10%, TA=-40 to 125°C; IOH = -2mA; Fig 8-2 | 9 | ||
| Output impedance ZO | ZO | 50 | Ω | Normal isolator channel; footnote 2 | 9 | ||
| Junction-to-ambient thermal resistance RθJA (SOIC16-WB) | RθJA | 83.4 | °C/W | IC junction-to-ambient, SOIC16-WB (W) package | 6 |
CAD (KiCad official)
- Symbol:
CA-IS3740LW - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
ca-is3740lw-etched.step/ca-is3740lw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3740lw.step/ca-is3740lw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (25 pp, sha256
fd7bb5373a55db4c, retrieved 2026-10-28, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).