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PIC18F6622-I
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPIC18F6622-I
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)
PIC18F6622-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RE1/WR/P2C | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port write control input (WR) and ECCP2 Enhanced PWM output C. |
| 2 | RE0/RD/P2D | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port read control input (RD) and ECCP2 Enhanced PWM output D. |
| 3 | RG0/ECCP3/P3A | bidirectional | Digital I/O; Enhanced Capture 3 input/Compare 3 output/PWM 3 output (ECCP3) and ECCP3 PWM output A (P3A). |
| 4 | RG1/TX2/CK2 | bidirectional | Digital I/O; EUSART2 asynchronous transmit (TX2) and EUSART2 synchronous clock (CK2). |
| 5 | RG2/RX2/DT2 | bidirectional | Digital I/O; EUSART2 asynchronous receive (RX2) and EUSART2 synchronous data (DT2). |
| 6 | RG3/CCP4/P3D | bidirectional | Digital I/O; CCP4 capture input/compare output/PWM output and ECCP3 PWM output D (P3D). |
| 7 | RG5/MCLR/VPP | input | Active-low Master Clear (Reset) input when MCLRE is set; otherwise a digital input only, and the programming voltage input (VPP) for ICSP mode entry. |
| 8 | RG4/CCP5/P1D | bidirectional | Digital I/O; CCP5 capture input/compare output/PWM output and ECCP1 PWM output D (P1D). |
| 9 | VSS | power_in | Ground reference for logic and I/O pins. |
| 10 | VDD | power_in | Positive supply for logic and I/O pins. |
| 11 | RF7/SS1 | bidirectional | Digital I/O (Schmitt Trigger input); SPI slave select input for MSSP1 (TTL input). |
| 12 | RF6/AN11 | bidirectional | Digital I/O; analog input 11 for the A/D converter and Comparator C1- input. |
| 13 | RF5/AN10/CVREF | bidirectional | Digital I/O; analog input 10 for the A/D converter and Comparator C1+ input, with comparator voltage reference output CVREF. |
| 14 | RF4/AN9 | bidirectional | Digital I/O; analog input 9 for the A/D converter and Comparator C2- input. |
| 15 | RF3/AN8 | bidirectional | Digital I/O; analog input 8 for the A/D converter and Comparator C2+ input. |
| 16 | RF2/AN7/C1OUT | bidirectional | Digital I/O; analog input 7 for the A/D converter and Comparator 1 output (C1OUT). |
| 17 | RF1/AN6/C2OUT | bidirectional | Digital I/O; analog input 6 for the A/D converter and Comparator 2 output (C2OUT). |
| 18 | RF0/AN5 | bidirectional | Digital I/O; analog input 5 for the A/D converter. |
| 19 | AVDD | power_in | Positive supply for analog modules. |
| 20 | AVSS | power_in | Ground reference for analog modules. |
| 21 | RA3/AN3/VREF+ | bidirectional | Digital I/O (TTL input); analog input 3 and A/D reference voltage (high) input VREF+. |
| 22 | RA2/AN2/VREF- | bidirectional | Digital I/O (TTL input); analog input 2 and A/D reference voltage (low) input VREF-. |
| 23 | RA1/AN1 | bidirectional | Digital I/O (TTL input); analog input 1 for the A/D converter. |
| 24 | RA0/AN0 | bidirectional | Digital I/O (TTL input); analog input 0 for the A/D converter. |
| 25 | VSS | power_in | Ground reference for logic and I/O pins. |
| 26 | VDD | power_in | Positive supply for logic and I/O pins. |
| 27 | RA5/AN4/HLVDIN | bidirectional | Digital I/O (TTL input); analog input 4 and High/Low-Voltage Detect input (HLVDIN). |
| 28 | RA4/T0CKI | bidirectional | Digital I/O (Schmitt Trigger input); Timer0 external clock input (T0CKI). |
| 29 | RC1/T1OSI/ECCP2/P2A | bidirectional | Digital I/O (Schmitt Trigger input); Timer1 oscillator input (T1OSI) and, by default when CCP2MX is set, ECCP2 capture/compare/PWM pin with ECCP2 PWM output A (P2A). |
| 30 | RC0/T1OSO/T13CKI | bidirectional | Digital I/O (Schmitt Trigger input); Timer1 oscillator output (T1OSO) and Timer1/Timer3 external clock input (T13CKI). |
| 31 | RC6/TX1/CK1 | bidirectional | Digital I/O (Schmitt Trigger input); EUSART1 asynchronous transmit (TX1) and EUSART1 synchronous clock (CK1). |
| 32 | RC7/RX1/DT1 | bidirectional | Digital I/O (Schmitt Trigger input); EUSART1 asynchronous receive (RX1) and EUSART1 synchronous data (DT1). |
| 33 | RC2/ECCP1/P1A | bidirectional | Digital I/O (Schmitt Trigger input); Enhanced Capture 1 input/Compare 1 output/PWM 1 output (ECCP1) and ECCP1 PWM output A (P1A). |
| 34 | RC3/SCK1/SCL1 | bidirectional | Digital I/O (Schmitt Trigger input); MSSP1 synchronous serial clock for SPI mode (SCK1) and I2C mode (SCL1). |
| 35 | RC4/SDI1/SDA1 | bidirectional | Digital I/O (Schmitt Trigger input); MSSP1 SPI data input (SDI1) and I2C data I/O (SDA1). |
| 36 | RC5/SDO1 | bidirectional | Digital I/O (Schmitt Trigger input); MSSP1 SPI data output (SDO1). |
| 37 | RB7/KBI3/PGD | bidirectional | Digital I/O with weak pull-up; interrupt-on-change pin KBI3 and In-Circuit Debugger/ICSP programming data pin (PGD). |
| 38 | VDD | power_in | Positive supply for logic and I/O pins. |
| 39 | OSC1/CLKI/RA7 | bidirectional | Oscillator crystal or external clock input (OSC1/CLKI); when not used as oscillator, general purpose I/O pin RA7. |
| 40 | OSC2/CLKO/RA6 | bidirectional | Oscillator crystal output connecting to a crystal or resonator; in RC mode it outputs CLKO (FOSC/4), otherwise general purpose I/O pin RA6. |
| 41 | VSS | power_in | Ground reference for logic and I/O pins. |
| 42 | RB6/KBI2/PGC | bidirectional | Digital I/O with weak pull-up; interrupt-on-change pin KBI2 and In-Circuit Debugger/ICSP programming clock pin (PGC). |
| 43 | RB5/KBI1/PGM | bidirectional | Digital I/O with weak pull-up; interrupt-on-change pin KBI1 and Low-Voltage ICSP programming enable pin (PGM). |
| 44 | RB4/KBI0 | bidirectional | Digital I/O with weak pull-up; interrupt-on-change pin KBI0. |
| 45 | RB3/INT3 | bidirectional | Digital I/O with weak pull-up; external interrupt 3 (INT3). |
| 46 | RB2/INT2 | bidirectional | Digital I/O with weak pull-up; external interrupt 2 (INT2). |
| 47 | RB1/INT1 | bidirectional | Digital I/O with weak pull-up; external interrupt 1 (INT1). |
| 48 | RB0/INT0/FLT0 | bidirectional | Digital I/O with weak pull-up; external interrupt 0 (INT0) and ECCPx PWM Fault input (FLT0). |
| 49 | RD7/PSP7/SS2 | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port data bit 7 (PSP7) and MSSP2 SPI slave select input (SS2). |
| 50 | RD6/PSP6/SCK2/SCL2 | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port data bit 6 (PSP6), MSSP2 SPI clock (SCK2) and I2C clock (SCL2). |
| 51 | RD5/PSP5/SDI2/SDA2 | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port data bit 5 (PSP5), MSSP2 SPI data input (SDI2) and I2C data (SDA2). |
| 52 | RD4/PSP4/SDO2 | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port data bit 4 (PSP4) and MSSP2 SPI data output (SDO2). |
| 53 | RD3/PSP3 | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port data bit 3 (PSP3). |
| 54 | RD2/PSP2 | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port data bit 2 (PSP2). |
| 55 | RD1/PSP1 | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port data bit 1 (PSP1). |
| 56 | VSS | power_in | Ground reference for logic and I/O pins. |
| 57 | VDD | power_in | Positive supply for logic and I/O pins. |
| 58 | RD0/PSP0 | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port data bit 0 (PSP0). |
| 59 | RE7/ECCP2/P2A | bidirectional | Digital I/O (Schmitt Trigger input); alternate ECCP2 capture/compare/PWM pin with ECCP2 PWM output A (P2A) when CCP2MX is cleared. |
| 60 | RE6/P1B | bidirectional | Digital I/O (Schmitt Trigger input); ECCP1 Enhanced PWM output channel B (P1B). |
| 61 | RE5/P1C | bidirectional | Digital I/O (Schmitt Trigger input); ECCP1 Enhanced PWM output channel C (P1C). |
| 62 | RE4/P3B | bidirectional | Digital I/O (Schmitt Trigger input); ECCP3 Enhanced PWM output channel B (P3B). |
| 63 | RE3/P3C | bidirectional | Digital I/O (Schmitt Trigger input); ECCP3 Enhanced PWM output channel C (P3C). |
| 64 | RE2/CS/P2B | bidirectional | Digital I/O (Schmitt Trigger input); Parallel Slave Port chip select input (CS) and ECCP2 Enhanced PWM output channel B (P2B). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating frequency | 40 | MHz | Printed as DC, 40 MHz (Table 1-1) | 9 | |||
| RC oscillator external resistor | REXT | 3 | 100 | kΩ | RC and RCIO oscillator modes, recommended value | 35 | |
| RC oscillator external capacitor | CEXT | 20 | 300 | pF | RC and RCIO oscillator modes, recommended value | 35 | |
| MCLR pull-up resistor for POR | 1 | 10 | kΩ | MCLR tied to VDD through resistor to eliminate external POR RC components | 53 | ||
| External POR circuit resistor | R | 40 | kΩ | Slow VDD power-up external POR circuit; recommended so voltage drop does not violate electrical specification | 53 | ||
| Maximum recommended analog source impedance | RS | 2.5 | kΩ | A/D analog input source, recommended maximum | 276 |
CAD (KiCad official)
- Symbol:
PIC18F6622-I - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
pic18f6622-i-etched.step/pic18f6622-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic18f6622-i.step/pic18f6622-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (446 pp, sha256
3c49d4b5c2f54a31, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).