component
SY8501FCC
Public Unreviewedby Ray
Silergy Corp DC-DC Converters, SO-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSY8501FCC
Silergy Corp · DC-DC Converters · SO-8-EP
SY8501FCC from Silergy Corp, in a SO-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | Not connected. Leave floating or tie to a copper pour as convenient; no internal bond. |
| 2 | IN | power_in | Input supply pin, 7V to 100V operating range (110V absolute maximum). Decouple this pin to GND with a low-ESR ceramic capacitor placed close to the pin. |
| 3 | EN | input | Enable control input. Accurate 1.2V rising threshold (0.8V falling); can be driven directly or programmed via a resistor divider from VIN to set the VIN turn-on voltage. Absolute max VIN+0.3V. |
| 4 | RON | input | On-time programming pin. Connect a resistor from RON to IN to set the top-switch ON time and therefore the switching frequency (Fs [kHz] = 550 / Ron [MΩ], 200kHz-1000kHz range). Absolute max 6V. |
| 5 | FB | input | Output feedback pin. Connect to the mid-point of the output resistor divider to set Vout = 1.2V*(1 + R1/R2). Reference is the internal 1.2V (typ), +/-2% accurate. Absolute max 6V. |
| 6 | VCC | power_out | Output of the internal LDO (~4V VDD rail) used to supply internal gate-drive and control circuitry. Decouple to GND with a small ceramic capacitor (CVCC). Absolute max 30V. |
| 7 | BS | passive | Boot-strap pin that supplies the high-side gate driver. Connect a 0.1uF ceramic capacitor from BS to LX to develop the bootstrap voltage above LX. Absolute max LX+6V. |
| 8 | LX | power_out | Switching node / inductor pin. Connects to the drain of the top switch and source of the bottom switch; tie to the external inductor. Absolute max VIN+0.3V. |
| 9 | GND | power_in | Exposed thermal pad on the underside of the SO8E package. Serves as the device ground return and primary thermal path; solder to a large ground copper pour on the PCB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SO-8-EP |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
SY8501FCC
CAD (KiCad official)
- Symbol:
SY8501FCC - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8-EP (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (15 pp, sha256
7f2cd8e9af381554, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).