component
SY8089AAAC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSY8089AAAC
Silergy Corp · DC-DC Converters · SOT-23-5
SY8089AAAC from Silergy Corp, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable control input. Pull high (>1.5V) to turn on the regulator; pull low (<0.4V) to shut down (Ishdn ~0.1µA). Do not float; add a 1MΩ pull-down to GND if the driving source can go high-Z. |
| 2 | GND | power_in | Ground return pin. Maximize copper area for best thermal and noise performance; keep CIN loop area to IN/GND minimal. |
| 3 | LX | power_out | Switching node output; connect to the external inductor (typ. 2.2µH). Internal PFET (110mΩ) sources to VIN and NFET (80mΩ) sinks to GND; peak current limit 3.5A. Minimize PCB copper area on this node to reduce switching noise. |
| 4 | IN | power_in | Supply input, 2.7V to 5.5V (abs max 6.0V). Decouple to GND with at least a 10µF (typ. 22µF) X5R/X7R ceramic capacitor placed close to the IN and GND pins. |
| 5 | FB | input | Output voltage feedback input. Connect to the mid-point of the R1/R2 output divider to program Vout = 0.6V × (1 + R1/R2). Reference is 0.6V (±2%); IFB ±50nA. Keep FB trace away from the LX net. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | SOT-23-5 |
| Category | PMIC |
| Pins | 5 |
Ordering variants
Same part, different packaging or reel option.
SY8089AAACSY8089AAC
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 2.7 | 5.5 | V | 4 | ||
| Quiescent Current | IQ | 55 | µA | IOUT=0, VFB=VREF⋅105% | 4 | ||
| Shutdown Current | ISHDN | 0.1 | 1 | µA | EN=0 | 4 | |
| Feedback Reference Voltage | VREF | 0.588 | 0.6 | 0.612 | V | 4 | |
| FB Input Current | IFB | -50 | 50 | nA | VFB=VIN | 4 | |
| PFET RON | RDS(ON),P | 110 | mΩ | 4 | |||
| NFET RON | RDS(ON),N | 80 | mΩ | 4 | |||
| PFET Current Limit | ILIM | 3.5 | A | 4 | |||
| EN rising threshold | VENH | 1.5 | V | 4 | |||
| EN falling threshold | VENL | 0.4 | V | 4 | |||
| Input UVLO threshold | VUVLO | 2.5 | V | 4 | |||
| UVLO hysteresis | VHYS | 0.2 | V | 4 | |||
| Oscillator Frequency | FOSC | 1 | MHz | IOUT=500mA | 4 | ||
| Short Circuit Protection Latch Off Threshold | VSCP | 0.25 | V | 4 | |||
| Min ON Time | 75 | ns | 4 | ||||
| Max Duty Cycle | 100 | % | 4 | ||||
| Soft Start Time | TSS | 1.2 | ms | 4 | |||
| Output Discharge Switch On Resistance | RDISCH | 50 | Ω | 4 | |||
| Thermal Shutdown Temperature | TSD | 160 | °C | 4 | |||
| Supply Input Voltage (recommended) | 2.7 | 5.5 | V | 2 | |||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 2 | |||
| Ambient Temperature Range (recommended) | -40 | 85 | °C | 2 | |||
| Supply Input Voltage (absolute maximum) | -0.3 | 6 | V | 2 | |||
| Enable, FB Voltage (absolute maximum) | -0.3 | V | max VIN + 0.6 V | 2 | |||
| Power Dissipation | PD | 0.6 | W | TA = 25°C, SOT23-5 | 2 | ||
| Junction Temperature Range (absolute maximum) | -40 | 150 | °C | 2 | |||
| Lead Temperature (soldering) | 260 | °C | 10 sec. | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Package Thermal Resistance, junction-to-ambient | θJA | 170 | °C/W | Note 2: 2in x 2in FR-4, 2oz copper, thermal vias | 2 | ||
| Package Thermal Resistance, junction-to-case | θJC | 130 | °C/W | 2 |
CAD (KiCad official)
- Symbol:
SY8089AAAC - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
sy8089aaac-etched.step/sy8089aaac-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sy8089aaac.step/sy8089aaac.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
sy8089aaac.step |
85 KB | You want the bare part, or you mark your own boards. |
sy8089aaac-etched.step |
2.2 MB | You want the part with SY8089AAAC already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 515 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (10 pp, sha256
be137413d9493bb7, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).