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DS75S+T&R
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Analog Devices Inc Maxim Integrated Temperature Sensors, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownDS75S+T&R
Analog Devices Inc Maxim Integrated · Temperature Sensors · SO-8
DS75S+T&R from Analog Devices Inc Maxim Integrated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDA | bidirectional | Data input/output pin for the 2-wire serial communication port, open drain. |
| 2 | SCL | input | Clock input pin for the 2-wire serial communication port. |
| 3 | O.S. | output | Open-drain thermostat output; it is active low at power-up (POL = 0) and can be changed to active high via the POL bit. |
| 4 | GND | power_in | Ground pin. |
| 5 | A2 | input | Address input pin that sets bit A2 of the 7-bit bus address (1 0 0 1 A2 A1 A0). |
| 6 | A1 | input | Address input pin that sets bit A1 of the 7-bit bus address (1 0 0 1 A2 A1 A0). |
| 7 | A0 | input | Address input pin that sets bit A0 of the 7-bit bus address (1 0 0 1 A2 A1 A0). |
| 8 | VDD | power_in | Supply voltage pin; the supply range is +2.7V to +5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | SO-8 |
| Category | Sensors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 2.7 | 5.5 | V | 4 | ||
| Voltage on VDD, Relative to Ground | VDD | -0.3 | 7 | V | Relative to Ground | 4 | |
| Voltage on any other pin, Relative to Ground | -0.3 | V | Relative to Ground; max printed as VDD + 0.3V | 4 | |||
| Operating Temperature | -55 | 125 | °C | 4 | |||
| Storage Temperature | -55 | 125 | °C | 4 | |||
| Soldering Temperature | 260 | °C | for 10s | 4 | |||
| Thermometer Error | TERR | -2 | 2 | °C | -25 to +100 (Note 2) | 4 | |
| Thermometer Error | TERR | -3 | 3 | °C | -55 to +125 (Note 2) | 4 | |
| Input Logic Low | VIL | -0.5 | V | (Note 1); max printed as 0.3 x VDD | 4 | ||
| SDA Output Logic Low Voltage | VOL1 | 0 | 0.4 | V | 3mA sink current (Note 1) | 4 | |
| SDA Output Logic Low Voltage | VOL2 | 0 | 0.6 | V | 6mA sink current (Note 1) | 4 | |
| O.S. Saturation Voltage | VOL | 0.8 | V | 4mA sink current (Notes 1, 2) | 4 | ||
| Input current each I/O pin | -10 | 10 | µA | 0.4 < VI/O< 0.9 VDD | 4 | ||
| I/O Capacitance | CI/O | 10 | pF | 4 | |||
| Standby Current | IDD1 | 1 | µA | (Notes 3, 4) | 4 | ||
| Active Current | IDD | 1000 | µA | Active temp conversions (Notes 3, 4) | 4 | ||
| Active Current | IDD | 100 | µA | Communication only (Notes 3, 4) | 4 | ||
| Resolution | 9 | 12 | bits | 5 | |||
| Temperature Conversion Time | tCONVT | 150 | ms | 9-bit conversions | 5 | ||
| Temperature Conversion Time | tCONVT | 300 | ms | 10-bit conversions | 5 | ||
| Temperature Conversion Time | tCONVT | 600 | ms | 11-bit conversions | 5 | ||
| Temperature Conversion Time | tCONVT | 1200 | ms | 12-bit conversions | 5 | ||
| SCL Frequency | fSCL | 400 | kHz | 5 | |||
| Bus Free Time Between a STOP and START Condition | tBUF | 1.3 | µs | (Note 5) | 5 | ||
| START and Repeated START Hold Time from Falling SCL | tHD:STA | 0.6 | µs | (Notes 5, 6) | 5 | ||
| Low Period of SCL | tLOW | 1.3 | µs | (Note 5) | 5 | ||
| High Period of SCL | tHIGH | 0.6 | µs | (Note 5) | 5 | ||
| Repeated START Condition Setup Time to Rising SCL | tSU:STA | 0.6 | µs | (Note 5) | 5 | ||
| Data-Out Hold Time from Falling SCL | tHD:DAT | 0 | 0.9 | µs | (Note 5) | 5 | |
| Data-In Setup Time to Rising SCL | tSU:DAT | 100 | ns | (Note 5) | 5 | ||
| Rise Time of SDA and SCL | tR | 1000 | ns | (Notes 5, 7); min printed as 20 + 0.1CB | 5 | ||
| Fall Time of SDA and SCL | tF | 300 | ns | (Notes 5, 7); min printed as 20 + 0.1CB | 5 | ||
| STOP Setup Time to Rising SCL | tSU:STO | 0.6 | µs | (Note 5) | 5 | ||
| Capacitive Load for Each Bus Line | CB | 400 | pF | 5 | |||
| Input Capacitance | CI | 5 | pF | 5 |
CAD (KiCad official)
- Symbol:
DS75S+T&R - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
ds75s-t-r-etched.step/ds75s-t-r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds75s-t-r.step/ds75s-t-r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices Inc Maxim Integrated datasheet (14 pp, sha256
4d52ae4058db4494, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).