component
EMC2101-R-ACZL-TR
Public Made by Adomby adom
Microchip Tech Temperature Sensors, MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownEMC2101-R-ACZL-TR
Microchip Tech · Temperature Sensors · MSOP-8
EMC2101-R-ACZL-TR from Microchip Tech, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | 3.3V power supply input for the device. |
| 2 | DP | input | External diode positive (anode) connection, used as an analog input for the remote temperature diode. |
| 3 | DN | input | External diode negative (cathode) connection, used as an analog input for the remote temperature diode. |
| 4 | FAN | output | Open-drain 5V-tolerant PWM output by default, or analog DAC output (0V to VDD) when selected in software. |
| 5 | GND | power_in | Ground reference pin for the device. |
| 6 | ALERT/TACH | bidirectional | Open-drain, 5V-tolerant active-low interrupt (ALERT) output that requires a pull-up resistor, or a TACH input; the pull-up value also selects the auto-configuration mode per Table 4-1. |
| 7 | SMDATA | bidirectional | SMBus data input/output; digital I/O that is open drain when used as an output, requires a pull-up resistor, and is 5V tolerant. |
| 8 | SMCLK | bidirectional | SMBus clock input; digital I/O that is open drain when used as an output, requires a pull-up resistor, and is 5V tolerant. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | MSOP-8 |
| Category | Sensors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute maximum) | VDD | -0.3 | 5 | V | 3 | ||
| Voltage on 5V tolerant pins | V5VT_pin | -0.3 | 5.5 | V | 3 | ||
| Voltage on 5V tolerant pins /V5VT_pin - VDD/ | /V5VT_pin -VDD/ | -0.3 | 3.6 | V | (Note) | 3 | |
| Operating Temperature Range | -40 | 125 | °C | 3 | |||
| Storage Temperature Range | -55 | 150 | °C | 3 | |||
| Supply Voltage (recommended operating) | VDD | 3 | 3.3 | 3.6 | V | 3 | |
| Internal Temperature Accuracy | -2 | 1 | 2 | °C | 3 | ||
| External Temperature Accuracy | -1 | 0.5 | 1 | °C | +60°C < TDIODE < +100°C; 10°C < TA < +70°C | 4 | |
| External Temperature Accuracy | -3 | 1 | 3 | °C | 0°C < TDIODE < +125°C | 4 | |
| TACH Accuracy | 10 | % | TACH valid | 4 | |||
| Supply Current | IDD | 0.6 | 1 | mA | 16 conversion/second, PWM or DAC driver operational | 3 | |
| Supply Current | IDD | 300 | 400 | µA | Temp monitoring disabled, DAC driver enabled, no load | 3 | |
| Standby Current | ISTANDBY | 270 | µA | PWM disabled, monitoring disabled | 3 | ||
| Diode Decoupling Capacitor (external diode) | CFILTER | 2.2 | nF | Connected across External Diode (2N3904) | 4 | ||
| Diode Decoupling Capacitor (substrate transistor) | CFILTER | 470 | pF | Connected across Substrate Transistor (CPU diode) | 4 | ||
| PWM Frequency | fPWM | 22 | Hz | For 64 steps, higher frequencies are possible with reduced resolution (see Appendix B) | 4 | ||
| PWM Duty Cycle | DPWM | 0 | 100 | % | 4 | ||
| Output Low Voltage | VOL | 0.3 | V | 8 mA Current Sink | 4 | ||
| Output Leakage Current | ILEAK | 10 | µA | Device powered or unpowered; TA < +85°C; Pull-up voltage ≤ 3.6V | 4 | ||
| SMBus Input High Voltage | VIH | 2.1 | V | 5 | |||
| SMBus Input Low Voltage | VIL | 0.8 | V | 5 | |||
| SMBus Input High/Low Current | IIH/IIL | -1 | 1 | µA | 5 | ||
| SMBus Clock Frequency | fSMB | 10 | 400 | kHz | 5 | ||
| SMBus Spike Suppression | tSP | 50 | ns | 5 | |||
| SMBus Bus free time Start to Stop | tBUF | 1.3 | µs | 5 | |||
| SMBus Hold Time: Start | tHD:STA | 0.6 | µs | 5 | |||
| SMBus Setup Time: Start | tSU:STA | 0.6 | µs | 5 | |||
| SMBus Setup Time: Stop | tSU:STO | 0.6 | µs | 5 | |||
| SMBus Data Hold Time | tHD:DAT | 0.3 | µs | 5 | |||
| SMBus Data Setup Time | tSU:DAT | 100 | ns | 5 | |||
| SMBus Clock Low Period | tLOW | 1.3 | µs | 5 | |||
| SMBus Clock High Period | tHIGH | 0.6 | µs | 5 | |||
| SMBus Clock/Data Fall Time | tFALL | 300 | ns | Min = 20+0.1CLOAD ns | 5 | ||
| SMBus Clock/Data Rise Time | tRISE | 300 | ns | Min = 20+0.1CLOAD ns (Note 1) | 5 | ||
| SMBus Capacitive Load | CLOAD | 400 | pF | Per bus line | 5 | ||
| EEPROM Loader Input High Voltage | VIH | 2.1 | V | 5 | |||
| EEPROM Loader Input Low Voltage | VIL | 0.8 | V | 5 | |||
| EEPROM Loader Input High/Low Current | IIH/IIL | -1 | 1 | µA | 5 | ||
| EEPROM Loader Spike Suppression | tSP | 50 | ns | 6 | |||
| EEPROM Loader Bus free time Start to Stop | tBUF | 1.3 | µs | 6 | |||
| EEPROM Loader Hold Time: Start | tHD:STA | 0.6 | µs | 6 | |||
| EEPROM Loader Setup Time: Start | tSU:STA | 0.6 | µs | 6 | |||
| EEPROM Loader Setup Time: Stop | tSU:STO | 0.6 | µs | 6 | |||
| EEPROM Loader Data Hold Time | tHD:DAT | 0.3 | µs | 6 | |||
| EEPROM Loader Data Setup Time | tSU:DAT | 100 | ns | 6 | |||
| EEPROM Loader Clock Low Period | tLOW | 1.3 | µs | 6 | |||
| EEPROM Loader Clock High Period | tHIGH | 0.6 | µs | 6 | |||
| EEPROM Loader Clock/Data Fall Time | tFALL | 300 | ns | Min = 20+0.1 CLOAD ns | 6 | ||
| EEPROM Loader Clock/Data Rise Time | tRISE | 300 | ns | Min = 20+0.1 CLOAD ns | 6 | ||
| EEPROM Loader Capacitive Load | CLOAD | 400 | pF | Per bus line | 6 | ||
| Supply Current | IDD | 200 | µA | 1 conversion/16 seconds, PWM driver operational | 3 | ||
| Supply Current | IDD | 300 | µA | 1 conversion/16 seconds, DAC driver, no load | 3 | ||
| Conversion Time Internal Channel | tCONV | 3 | ms | 3 | |||
| Conversion Time External Channel | tCONV | 21 | ms | 4 | |||
| Resistance Error Correction Series Resistance | RSERIES | 100 | Ω | Series resistance in DP and DN lines | 4 | ||
| Total Unadjusted Error | TUE | 5 | % | Measured at 3/4 full scale | 4 | ||
| EEPROM Loading Delay | tDLY | 10 | ms | Delay after power-up until EEPROM loading begins | 6 | ||
| EEPROM Loading Time | tLOAD | 50 | ms | 6 |
CAD (KiCad official)
- Symbol:
EMC2101-R-ACZL-TR - Footprint:
Package_SO:MSOP-8_3x3mm_P0.65mm - 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files:
emc2101-r-aczl-tr-etched.step/emc2101-r-aczl-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);emc2101-r-aczl-tr.step/emc2101-r-aczl-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (56 pp, sha256
1e5b0fc888d463b6, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).