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TLC2652AIP

Public Made by Adom

by adom

Texas Instruments Precision Op Amps, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TLC2652AIP

Texas Instruments · Precision Op Amps · PDIP-8

TLC2652AIP from Texas Instruments, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CXA passive External chopper capacitor pin: a 0.1 µF to 1 µF capacitor should be placed as close as possible to this pin and returned to VDD−.
2 IN− input Inverting input, with differential input voltage limited to ±16 V and input current limited to ±5 mA.
3 IN+ input Noninverting input; the common-mode input range includes the negative rail and extends up to VDD+ − 1.9 V.
4 VDD− power_in Negative supply rail, with a maximum of −8 V relative to the midpoint between VDD+ and VDD−.
5 CLAMP passive Optional output clamp pin that reduces overload recovery time; the internal clamp switch activates when the output is about 1 V from either supply rail.
6 OUT output Amplifier output, with maximum peak output swing of about ±4.7 V at RL = 10 kΩ and ±5 V supplies.
7 VDD+ power_in Positive supply rail, with operating supply range ±1.9 V to ±8 V and a maximum of 8 V.
8 CXB passive External chopper capacitor pin: a 0.1 µF to 1 µF capacitor should be placed as close as possible to this pin and returned to VDD−.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD+ (absolute maximum) VDD+ 8 V see Note 1 4
Supply voltage VDD− (absolute maximum) VDD− -8 V see Note 1 4
Differential input voltage VID -16 16 V see Note 2 4
Input voltage (any input) VI -8 8 V any input, see Note 1 4
Voltage range on CLK IN and INT/EXT 5.2 V VDD− to VDD− + 5.2 V (relative to VDD−) 4
Input current (each input) II -5 5 mA each input 4
Output current IO -50 50 mA 4
Current into CLK IN and INT/EXT -5 5 mA 4
Operating free-air temperature (I suffix) TA -40 85 °C I suffix 4
Storage temperature range Tstg -65 150 °C 4
Lead temperature 260 °C 1,6 mm from case for 10 seconds, D, N, or P package 4
Supply voltage VDD± 1.9 8 V I suffix; magnitude of ±VDD 4
Clock input voltage 5 V I suffix; relative to VDD−, min VDD− 4
Operating free-air temperature TA -40 85 °C I suffix 4
Input offset voltage VIO 0.5 1 µV TA = 25°C, VDD± = ±5 V 7
Input offset voltage (full range) VIO 2.95 µV Full range, TA = −40°C to 85°C, VDD± = ±5 V 7
Temperature coefficient of input offset voltage αVIO 0.003 0.03 µV/°C Full range, TA = −40°C to 85°C 7
Input offset voltage long-term drift 0.003 0.02 µV/mo VIC = 0, RS = 50 Ω, TA = 25°C 7
Input offset current IIO 2 60 pA TA = 25°C 7
Input offset current (full range) IIO 150 pA Full range, TA = −40°C to 85°C 7
Input bias current IIB 4 60 pA TA = 25°C 7
Input bias current (full range) IIB 150 pA Full range, TA = −40°C to 85°C 7
Common-mode input voltage range VICR -5 3.1 V RS = 50 Ω, Full range 7
Maximum positive peak output voltage swing VOM+ 4.7 4.8 V RL = 10 kΩ, See Note 5, TA = 25°C 7
Maximum positive peak output voltage swing (full range) VOM+ 4.7 V RL = 10 kΩ, See Note 5, Full range 7
Maximum negative peak output voltage swing VOM− -4.7 -4.9 V RL = 10 kΩ, See Note 5, TA = 25°C 7
Maximum negative peak output voltage swing (full range) VOM− -4.7 V RL = 10 kΩ, See Note 5, Full range 7
Large-signal differential voltage amplification AVD 135 150 dB VO = ±4 V, RL = 10 kΩ, TA = 25°C 7
Large-signal differential voltage amplification (full range) AVD 125 dB VO = ±4 V, RL = 10 kΩ, Full range 7
Common-mode rejection ratio CMRR 120 140 dB VO = 0, VIC = VICRmin, TA = 25°C 7
Common-mode rejection ratio (full range) CMRR 120 dB VO = 0, VIC = VICRmin, RS = 50 Ω, Full range 7
Supply-voltage rejection ratio kSVR 110 135 dB VDD± = ±1.9 V to ±8 V, TA = 25°C 7
Supply-voltage rejection ratio (full range) kSVR 110 dB VDD± = ±1.9 V to ±8 V, VO = 0, RS = 50 Ω, Full range 7
Supply current IDD 1.5 2.4 mA VO = 0, No load, TA = 25°C 7
Supply current (full range) IDD 2.5 mA VO = 0, No load, Full range 7
Positive slew rate at unity gain SR+ 2 2.8 V/µs VO = ±2.3 V, RL = 10 kΩ, TA = 25°C 8
Positive slew rate at unity gain (full range) SR+ 1.4 V/µs VO = ±2.3 V, RL = 10 kΩ, Full range 8
Negative slew rate at unity gain SR− 2.3 3.1 V/µs RL = 10 kΩ, CL = 100 pF, TA = 25°C 8
Negative slew rate at unity gain (full range) SR− 1.7 V/µs RL = 10 kΩ, CL = 100 pF, Full range 8
Equivalent input noise voltage Vn 94 140 nV/√Hz f = 10 Hz, TA = 25°C 8
Equivalent input noise voltage Vn 23 35 nV/√Hz f = 1 kHz, TA = 25°C 8

CAD (KiCad official)

  • Symbol: TLC2652AIP
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: tlc2652aip-etched.step / tlc2652aip-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc2652aip.step / tlc2652aip.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 5ae9c4459b4f1528, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF