component
DS8570D10
Public Made by Adomby adom
DSTECH Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DFN3x3-10L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownDS8570D10
DSTECH · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN3x3-10L
DS8570D10 from DSTECH, in a DFN3x3-10L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulator output; VOUT is set by VOUT = VREF x (R1+R2)/R2 with VREF of 0.8V typical, and the output capacitor should be at least 10µF ceramic. |
| 2 | VOUT | power_out | Regulator output; VOUT is set by VOUT = VREF x (R1+R2)/R2 with VREF of 0.8V typical, and the output capacitor should be at least 10µF ceramic. |
| 3 | VOUT | power_out | Regulator output; VOUT is set by VOUT = VREF x (R1+R2)/R2 with VREF of 0.8V typical, and the output capacitor should be at least 10µF ceramic. |
| 4 | FB | input | Output voltage setting input; VOUT = VREF x (R1+R2)/R2, and R1 and R2 should each be more than 10kΩ to reduce power loss. |
| 5 | POK | output | Open-drain power-good output that goes high when VOUT reaches 90% of its rated value, and requires an external pull-up (100kΩ to VOUT suggested). |
| 6 | EN | input | Enable control input with logic-high at 1.2V minimum and logic-low at 0.4V maximum; the regulator is off when EN is low or floating because the pin is internally pulled low. |
| 7 | VIN | power_in | Input supply voltage, specified from 1V to 5.5V in the recommended operating conditions. |
| 8 | VIN | power_in | Input supply voltage, specified from 1V to 5.5V in the recommended operating conditions. |
| 9 | VIN | power_in | Input supply voltage, specified from 1V to 5.5V in the recommended operating conditions. |
| 10 | VCC | power_in | Control circuit supply voltage, specified from 3V to 5.5V with VCC greater than VOUT + 1.5V. |
| 11 | GND | power_in | Ground; the exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | DSTECH |
| Package | DFN3x3-10L |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC Operation Range | VDD | 3 | 5.5 | V | 5 | ||
| VCC POR Threshold | VPOR_VCC | 2.4 | 2.7 | 3 | V | VCC Rising | 5 |
| VCC POR Falling Hysteresis | VPOR_VCC | 0.15 | 0.2 | V | VCC Falling | 5 | |
| Quiescent Current | IQ | 0.6 | 1.2 | mA | EN on, no load | 5 | |
| Input Voltage Range | VIN | 1 | 5.5 | V | 5 | ||
| VIN POR Threshold | VPOR_VIN | 0.7 | 0.8 | 0.9 | V | VIN Rising | 5 |
| VIN POR Falling Hysteresis | VPOR_VIN | 0.15 | 0.2 | 0.25 | V | VIN Falling | 5 |
| Reference Voltage | VREF | 0.788 | 0.8 | 0.812 | V | 5 | |
| VOUT Load Regulation | VLOAD | 0.5 | 1 | % | IOUT = 1mA to 3A, VIN = VOUT + 1V | 5 | |
| OUT Line Regulation | VLINE | 0.2 | 0.6 | % | VCC = 3.6V to 5.5V, VIN = VOUT + 1V to 5V, IOUT = 1mA | 5 | |
| Dropout Voltage | VDROP | 250 | 350 | mV | IOUT = 2A | 5 | |
| Dropout Voltage | VDROP | 350 | 450 | mV | IOUT = 3A | 5 | |
| Current Limit | ILIM | 3.1 | 3.6 | 4.2 | A | VIN = 3.6V | 5 |
| Short Circuit Current | ISC | 1 | 1.4 | 1.8 | A | VOUT < 0.2V | 5 |
| POK Delay Time | 1 | 1.5 | mS | 5 | |||
| POK Sink Capability | VPOK | 0.2 | 0.4 | V | ISINK = 10mA | 5 | |
| EN Input Voltage Logic-High | VIH | 1.2 | V | 5 | |||
| EN Input Voltage Logic-Low | VIL | 0.4 | V | 5 | |||
| EN Delay Time | 0.3 | 0.85 | 1.4 | mS | 5 | ||
| VDD Pin Shutdown Current | ISHDN_VDD | 1 | uA | VEN = 0V | 6 | ||
| VIN Pin Shutdown Current | ISHDN_VIN | 1 | uA | VEN = 0V, VIN = 5V | 6 | ||
| Soft-Start Time | TSS | 1.9 | 2.8 | 3.75 | mS | 6 | |
| VIN & VCC to GND | -0.3 | 6 | V | to GND | 4 | ||
| VOUT to GND | -0.3 | 6 | V | to GND | 4 | ||
| Other to GND | -0.3 | 6 | V | to GND | 4 | ||
| Lead Temperature (Soldering) | 260 | °C | 10 sec. | 4 | |||
| Junction Temperature | 150 | °C | 4 | ||||
| Storage Temperature Range | -60 | 150 | °C | 4 | |||
| ESD Susceptibility HBM | 2 | KV | HBM | 4 | |||
| Input Voltage | VIN | 1 | 5.5 | V | 4 | ||
| Control Voltage | VCC | 3 | 5.5 | V | VCC > VOUT + 1.5V | 4 | |
| Junction Temperature Range | -40 | 125 | °C | 4 | |||
| Ambient Temperature Range | -40 | 85 | °C | 4 | |||
| Package Thermal Resistance DFN3x3-10L, θJA | θJA | 70 | °C/W | TA = 25°C, measured on DSTECH EVB board (Note 2) | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitors must be back to the DS8570 ground pin using as wide and as short of a copper trace as is practical. | 9 |
CAD (KiCad official)
- Symbol:
DS8570D10 - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN3x3-10L (KiCad packages3D, STEP)
- 3D model files:
ds8570d10-etched.step/ds8570d10-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ds8570d10.step/ds8570d10.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: DSTECH datasheet (11 pp, sha256
fb0319560326929d, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).