A5988GEVTR-T from Allegro MicroSystems, LLC, in a QFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	I04	input	Control input for bridge 4 current level (I0 bit); logic high VIN(1) ≥ 2 V, low ≤ 0.8 V.
2	OUT1A	output	DMOS full-bridge 1 output A, rated up to 1.6 A and 40 V.
3	SENSE1	passive	Sense resistor terminal for bridge 1; voltage must not exceed ±500 mV.
4	OUT1B	output	DMOS full-bridge 1 output B, rated up to 1.6 A and 40 V.
5	VBB1	power_in	Load supply voltage for bridges 1 and 2, operating range 8 to 40 V.
6	OUT2B	output	DMOS full-bridge 2 output B, rated up to 1.6 A and 40 V.
7	SENSE2	passive	Sense resistor terminal for bridge 2; voltage must not exceed ±500 mV.
8	OUT2A	output	DMOS full-bridge 2 output A, rated up to 1.6 A and 40 V.
9	PHASE4	input	Control input setting the current direction (phase) of bridge 4.
10	PHASE3	input	Control input setting the current direction (phase) of bridge 3.
11	SLEEPn	input	Active-low sleep mode input; low disables much of the internal circuitry including the charge pump, with sleep current <1 µA typical.
12	VREF1	input	Analog reference input for bridge 1 current trip level, operating range 0 to 1.5 V.
13	VREF2	input	Analog reference input for bridge 2 current trip level, operating range 0 to 1.5 V.
14	VREF3	input	Analog reference input for bridge 3 current trip level, operating range 0 to 1.5 V.
15	VREF4	input	Analog reference input for bridge 4 current trip level, operating range 0 to 1.5 V.
16	GND	power_in	Analog and digital ground; must be connected externally to PGND and the thermal pad under the device.
17	PHASE2	input	Control input setting the current direction (phase) of bridge 2.
18	PHASE1	input	Control input setting the current direction (phase) of bridge 1.
19	I14	input	Control input for bridge 4 current level (I1 bit); logic high VIN(1) ≥ 2 V, low ≤ 0.8 V.
20	OUT4A	output	DMOS full-bridge 4 output A, rated up to 1.6 A and 40 V.
21	SENSE4	passive	Sense resistor terminal for bridge 4; voltage must not exceed ±500 mV.
22	OUT4B	output	DMOS full-bridge 4 output B, rated up to 1.6 A and 40 V.
23	VBB2	power_in	Load supply voltage for bridges 3 and 4, operating range 8 to 40 V.
24	OUT3B	output	DMOS full-bridge 3 output B, rated up to 1.6 A and 40 V.
25	SENSE3	passive	Sense resistor terminal for bridge 3; voltage must not exceed ±500 mV.
26	OUT3A	output	DMOS full-bridge 3 output A, rated up to 1.6 A and 40 V.
27	I13	input	Control input for bridge 3 current level (I1 bit); logic high VIN(1) ≥ 2 V, low ≤ 0.8 V.
28	I12	input	Control input for bridge 2 current level (I1 bit); logic high VIN(1) ≥ 2 V, low ≤ 0.8 V.
29	I11	input	Control input for bridge 1 current level (I1 bit); logic high VIN(1) ≥ 2 V, low ≤ 0.8 V.
30	PGND	power_in	Power ground; must be connected externally to GND and the thermal pad under the device.
31	VCP	passive	Reservoir capacitor terminal; a 0.1 µF ceramic capacitor is required between VCP and VBBx.
32	CP1	passive	Charge pump capacitor terminal; a 0.1 µF ceramic capacitor is connected between CP1 and CP2.
33	CP2	passive	Charge pump capacitor terminal; a 0.1 µF ceramic capacitor is connected between CP1 and CP2.
34	I01	input	Control input for bridge 1 current level (I0 bit); logic high VIN(1) ≥ 2 V, low ≤ 0.8 V.
35	I02	input	Control input for bridge 2 current level (I0 bit); logic high VIN(1) ≥ 2 V, low ≤ 0.8 V.
36	I03	input	Control input for bridge 3 current level (I0 bit); logic high VIN(1) ≥ 2 V, low ≤ 0.8 V.
37	PAD	passive	Exposed pad for enhanced thermal performance; should be soldered to the PCB and connected together with GND and PGND.

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	QFN-36-EP(6x6)
Category	Power Management ICs
Pins	37

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Load Supply Voltage Range	VBB	8		40	V	Operating	4
Source driver on resistance	RDS(on)		500	600	mΩ	IOUT = -1.2 A, TJ = 25°C	4
Sink driver on resistance	RDS(on)		500	600	mΩ	IOUT = 1.2 A, TJ = 25°C	4
Output diode forward voltage	Vf			1.2	V	IOUT = 1.2 A	4
Output Leakage	IDSS	-20		20	µA	Outputs, VOUT = 0 to VBB	4
VBB Supply Current, outputs on	IBB			23	mA	IOUT = 0 mA, outputs on, PWM = 50 kHz, DC = 50%	4
VBB Supply Current, outputs off	IBB		13.7	16	mA	Outputs off	4
VBB Supply Current, sleep mode	IBB	-10	1	10	µA	Sleep mode; typ printed as <1	4
Output Driver Slew Rate	SROUT	50	100	150	ns	10% to 90%	4
Logic Input Voltage high	VIN(1)	2			V		4
Logic Input Voltage low	VIN(0)			0.8	V		4
Logic Input Current	IIN	-20	1	20	µA	VIN = 0 to 5 V; typ printed as <1	4
Logic Input Hysteresis	Vhys	150	300	500	mV		4
Sleep Rising Threshold		2.5	2.7	2.95	V		4
Sleep Falling Threshold			2.4		V		4
Sleep Hysteresis		250	325	450	mV		4
Sleep Input Current			100	150	µA		4
Crossover Delay	tCOD	250	425	1000	ns		4
Blank Time	tBLANK	0.7	1	1.3	µs		4
VREFx Pin Input Voltage Range	VREFx	0		1.5	V	Operating	4
VREFx Pin Reference Input Current	IREF	-1		1	μA	VREF = 1.5	4
Current Trip-Level Error, 100%	VERR	-5		5	%	VREF = 1.5, phase current = 100%	4
Current Trip-Level Error, 67%	VERR	-5		5	%	VREF = 1.5, phase current = 67%	4
Current Trip-Level Error, 33%	VERR	-15		15	%	VREF = 1.5, phase current = 33%	4
VBB UVLO Threshold	VUV(VBB)	7.3	7.6	7.9	V	VBB rising	4
VBB UVLO Hysteresis	VUV(VBB)hys	400	500	600	mV		4
Overcurrent Protection Threshold		1.6			A		4
Fault Output Voltage				0.5	V	IOUT = 1 mA	4
Fault Output Leakage Current				1	µA	No fault, VOUT = 5 V	4
Thermal Shutdown Temperature	TJTSD	155	165	175	°C		4
Thermal Shutdown Hysteresis	TJTSDhys		15		°C		4
Load Supply Voltage	VBB	-0.5		40	V		2
Output Current	IOUT			1.6	A	May be limited by duty cycle, ambient temperature, and heat sinking; do not exceed Junction Temperature of 150°C	2
Logic Input Voltage Range	VIN	-0.3		7	V		2
SENSEx Pin Voltage	VSENSEx			0.5	V		2
SENSEx Pin Voltage, pulsed	VSENSEx			2.5	V	Pulsed tw < 1 µs	2
VREFx Pin Voltage	VREFx			2.5	V		2
Operating Temperature Range	TA	-40		105	ºC	Range G	2
Junction Temperature	TJ(max)			150	ºC		2
Storage Temperature Range	Tstg	-40		125	ºC		2
Package Thermal Resistance	RθJA		27		ºC/W	EV package, 4-layer PCB based on JEDEC standard	2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	package height of 0.90 mm. The JP is a 7 mm × 7 mm 48-pin LQFP. Both packages are lead (Pb) free, with 100% matte-tin	1

CAD (KiCad official)

Symbol: A5988GEVTR-T
Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
3D model: QFN-36-EP(6x6) (KiCad packages3D, STEP)
3D model files: a5988gevtr-t-etched.step / a5988gevtr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a5988gevtr-t.step / a5988gevtr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (14 pp, sha256 df96e240d5e64639, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

A5988GEVTR-T

Verified A5988GEVTR-T

Verification log 1 record

3D Model

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Schematic Symbol

PCB Footprint

Datasheet

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