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PIC32MX564F128H-I
Public Made by Adomby adom
Microchip Tech MICROCHIP, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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README
markdownPIC32MX564F128H-I
Microchip Tech · MICROCHIP · TQFP-64(10x10)
PIC32MX564F128H-I from Microchip Tech, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PMD5/RE5 | bidirectional | PORTE I/O (RE5) with Parallel Master Port data bit 5 (TTL/ST buffer). |
| 2 | PMD6/RE6 | bidirectional | PORTE I/O (RE6) with Parallel Master Port data bit 6 (TTL/ST buffer). |
| 3 | PMD7/RE7 | bidirectional | PORTE I/O (RE7) with Parallel Master Port data bit 7 (TTL/ST buffer). |
| 4 | SCK2/U6TX/U3RTS/PMA5/CN8/RG6 | bidirectional | PORTG I/O (RG6) shared with SPI2 clock, UART6 transmit, UART3 ready-to-send, PMP address 5 and change notification CN8. |
| 5 | SDA4/SDI2/U3RX/PMA4/CN9/RG7 | bidirectional | PORTG I/O (RG7) shared with I2C4 data, SPI2 data in, UART3 receive, PMP address 4 and change notification CN9. |
| 6 | SCL4/SDO2/U3TX/PMA3/CN10/RG8 | bidirectional | PORTG I/O (RG8) shared with I2C4 clock, SPI2 data out, UART3 transmit, PMP address 3 and change notification CN10. |
| 7 | MCLR | input | Master Clear input, an active-low device Reset (Schmitt Trigger input) that is also used for programming and debugging. |
| 8 | SS2/U6RX/U3CTS/PMA2/CN11/RG9 | bidirectional | PORTG I/O (RG9) shared with SPI2 slave select, UART6 receive, UART3 clear-to-send, PMP address 2 and change notification CN11. |
| 9 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |
| 10 | VDD | power_in | Positive supply for peripheral logic and I/O pins (2.3V to 3.6V operating range). |
| 11 | AN5/C1IN+/VBUSON/CN7/RB5 | bidirectional | PORTB I/O (RB5) with analog input 5, Comparator 1 positive input, USB host/OTG bus power control output VBUSON and CN7. |
| 12 | AN4/C1IN-/CN6/RB4 | bidirectional | PORTB I/O (RB4) with analog input 4, Comparator 1 negative input and CN6. |
| 13 | AN3/C2IN+/CN5/RB3 | bidirectional | PORTB I/O (RB3) with analog input 3, Comparator 2 positive input and CN5. |
| 14 | AN2/C2IN-/CN4/RB2 | bidirectional | PORTB I/O (RB2) with analog input 2, Comparator 2 negative input and CN4. |
| 15 | PGEC1/AN1/VREF-/CVREF-/CN3/RB1 | bidirectional | PORTB I/O (RB1) with ICSP programming/debug clock channel 1, analog input 1, VREF- / CVREF- low reference input and CN3. |
| 16 | PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 | bidirectional | PORTB I/O (RB0) with ICSP programming/debug data channel 1, analog input 0, VREF+ / CVREF+ high reference input, PMP address 6 and CN2. |
| 17 | PGEC2/AN6/OCFA/RB6 | bidirectional | PORTB I/O (RB6) with ICSP programming/debug clock channel 2, analog input 6 and Output Compare Fault A input. |
| 18 | PGED2/AN7/RB7 | bidirectional | PORTB I/O (RB7) with ICSP programming/debug data channel 2 and analog input 7. |
| 19 | AVDD | power_in | Positive supply for analog modules; must be connected at all times, even if the ADC is not used. |
| 20 | AVSS | power_in | Ground reference for analog modules; must be connected at all times. |
| 21 | AN8/SS4/U5RX/U2CTS/C1OUT/RB8 | bidirectional | PORTB I/O (RB8) with analog input 8, SPI4 slave select, UART5 receive, UART2 clear-to-send and Comparator 1 output. |
| 22 | AN9/C2OUT/PMA7/RB9 | bidirectional | PORTB I/O (RB9) with analog input 9, Comparator 2 output and PMP address 7. |
| 23 | TMS/AN10/CVREFOUT/PMA13/RB10 | bidirectional | PORTB I/O (RB10) with JTAG test mode select, analog input 10, comparator voltage reference output and PMP address 13. |
| 24 | TDO/AN11/PMA12/RB11 | bidirectional | PORTB I/O (RB11) with JTAG test data output, analog input 11 and PMP address 12. |
| 25 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |
| 26 | VDD | power_in | Positive supply for peripheral logic and I/O pins (2.3V to 3.6V operating range). |
| 27 | TCK/AN12/PMA11/RB12 | bidirectional | PORTB I/O (RB12) with JTAG test clock input, analog input 12 and PMP address 11. |
| 28 | TDI/AN13/PMA10/RB13 | bidirectional | PORTB I/O (RB13) with JTAG test data input, analog input 13 and PMP address 10. |
| 29 | AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 | bidirectional | PORTB I/O (RB14) with analog input 14, SPI4 clock, UART5 transmit, UART2 ready-to-send, PMP address latch high and PMP address 1. |
| 30 | AN15/OCFB/PMALL/PMA0/CN12/RB15 | bidirectional | PORTB I/O (RB15) with analog input 15, Output Compare Fault B input, PMP address latch low, PMP address 0 and CN12. |
| 31 | AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 | bidirectional | PORTF I/O (RF4) with alternate CAN1 transmit, I2C5 data, SPI4 data in, UART2 receive, PMP address 9 and CN17. |
| 32 | AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 | bidirectional | PORTF I/O (RF5) with alternate CAN1 receive, I2C5 clock, SPI4 data out, UART2 transmit, PMP address 8 and CN18. |
| 33 | USBID/RF3 | bidirectional | PORTF I/O (RF3) with USB OTG ID detect input. |
| 34 | VBUS | power_in | USB bus power monitor analog input. |
| 35 | VUSB3V3 | power_in | USB internal transceiver supply; must be connected to VDD if the USB module is not used. |
| 36 | D-/RG3 | bidirectional | USB D- analog data line (RG3 input). |
| 37 | D+/RG2 | bidirectional | USB D+ analog data line (RG2 input). |
| 38 | VDD | power_in | Positive supply for peripheral logic and I/O pins (2.3V to 3.6V operating range). |
| 39 | OSC1/CLKI/RC12 | bidirectional | Primary oscillator crystal input or external clock source input (ST buffer in RC mode, CMOS otherwise), also PORTC I/O RC12. |
| 40 | OSC2/CLKO/RC15 | bidirectional | Primary oscillator crystal output, optionally CLKO in RC and EC modes, also PORTC I/O RC15. |
| 41 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |
| 42 | RTCC/IC1/INT1/RD8 | bidirectional | PORTD I/O (RD8) with RTCC alarm output, Input Capture 1 and External Interrupt 1. |
| 43 | SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 | bidirectional | PORTD I/O (RD9) with SPI3 slave select, UART4 receive, UART1 clear-to-send, I2C1 data, Input Capture 2 and External Interrupt 2. |
| 44 | SCL1/IC3/PMCS2/PMA15/INT3/RD10 | bidirectional | PORTD I/O (RD10) with I2C1 clock, Input Capture 3, PMP chip select 2 / address 15 and External Interrupt 3. |
| 45 | IC4/PMCS1/PMA14/INT4/RD11 | bidirectional | PORTD I/O (RD11) with Input Capture 4, PMP chip select 1 / address 14 and External Interrupt 4. |
| 46 | OC1/INT0/RD0 | bidirectional | PORTD I/O (RD0) with Output Compare 1 output and External Interrupt 0. |
| 47 | SOSCI/CN1/RC13 | bidirectional | 32.768 kHz secondary oscillator crystal input (ST, CMOS otherwise) with CN1 and PORTC I/O RC13. |
| 48 | SOSCO/T1CK/CN0/RC14 | bidirectional | 32.768 kHz secondary oscillator crystal output with Timer1 external clock input, CN0 and PORTC I/O RC14. |
| 49 | SCK3/U4TX/U1RTS/OC2/RD1 | bidirectional | PORTD I/O (RD1) with SPI3 clock, UART4 transmit, UART1 ready-to-send and Output Compare 2. |
| 50 | SDA3/SDI3/U1RX/OC3/RD2 | bidirectional | PORTD I/O (RD2) with I2C3 data, SPI3 data in, UART1 receive and Output Compare 3. |
| 51 | SCL3/SDO3/U1TX/OC4/RD3 | bidirectional | PORTD I/O (RD3) with I2C3 clock, SPI3 data out, UART1 transmit and Output Compare 4. |
| 52 | OC5/IC5/PMWR/CN13/RD4 | bidirectional | PORTD I/O (RD4) with Output Compare 5, Input Capture 5, PMP write strobe and CN13. |
| 53 | PMRD/CN14/RD5 | bidirectional | PORTD I/O (RD5) with PMP read strobe and CN14. |
| 54 | CN15/RD6 | bidirectional | PORTD I/O (RD6) with change notification input CN15. |
| 55 | CN16/RD7 | bidirectional | PORTD I/O (RD7) with change notification input CN16. |
| 56 | VCAP | passive | Capacitor connection for the internal voltage regulator; needs a low-ESR capacitor to ground and must not be connected to VDD. |
| 57 | VDD | power_in | Positive supply for peripheral logic and I/O pins (2.3V to 3.6V operating range). |
| 58 | C1RX/RF0 | bidirectional | PORTF I/O (RF0) with CAN1 bus receive input. |
| 59 | C1TX/RF1 | bidirectional | PORTF I/O (RF1) with CAN1 bus transmit output. |
| 60 | PMD0/RE0 | bidirectional | PORTE I/O (RE0) with Parallel Master Port data bit 0 (TTL/ST buffer). |
| 61 | PMD1/RE1 | bidirectional | PORTE I/O (RE1) with Parallel Master Port data bit 1 (TTL/ST buffer). |
| 62 | PMD2/RE2 | bidirectional | PORTE I/O (RE2) with Parallel Master Port data bit 2 (TTL/ST buffer). |
| 63 | PMD3/RE3 | bidirectional | PORTE I/O (RE3) with Parallel Master Port data bit 3 (TTL/ST buffer). |
| 64 | PMD4/RE4 | bidirectional | PORTE I/O (RE4) with Parallel Master Port data bit 4 (TTL/ST buffer). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 2.3 | 3.6 | V | 357 | ||
| RAM Data Retention Voltage | VDR | 1.75 | V | 357 | |||
| VDD Start Voltage to Ensure Internal Power-on Reset Signal | VPOR | 1.75 | 2.1 | V | 357 | ||
| VDD Rise Rate to Ensure Internal Power-on Reset Signal | SVDD | 5e-05 | 0.115 | V/s | 357 | ||
| Operating temperature (Industrial) | TA | -40 | 85 | °C | Industrial | 357 | |
| Ambient temperature under bias | -40 | 105 | °C | 355 | |||
| Storage temperature | -65 | 150 | °C | 355 | |||
| Voltage on VDD with respect to VSS | VDD | -0.3 | 4 | V | 355 | ||
| Voltage on any pin that is not 5V tolerant, with respect to VSS | -0.3 | V | max is VDD + 0.3V; Note 3 | 355 | |||
| Voltage on any 5V tolerant pin with respect to VSS | -0.3 | 5.5 | V | VDD ≥ 2.3V (Note 3) | 355 | ||
| Voltage on any 5V tolerant pin with respect to VSS | -0.3 | 3.6 | V | VDD < 2.3V (Note 3) | 355 | ||
| Voltage on VBUS with respect to VSS | VBUS | -0.3 | 5.5 | V | 355 |
CAD (KiCad official)
- Symbol:
PIC32MX564F128H-I - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
pic32mx564f128h-i-etched.step/pic32mx564f128h-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic32mx564f128h-i.step/pic32mx564f128h-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheetDatasheet_DS60001156K.pdf) (446 pp, sha256
2413ac5834b12306, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).