Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

MC74HCT08ADTR2G

onsemi · Gates · TSSOP-14

MC74HCT08ADTR2G from onsemi, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Gate 1, input A. LSTTL-compatible CMOS logic input; V_IH >= 2.0 V, V_IL <= 0.8 V at V_CC = 4.5-5.5 V. Input leakage +/-1 uA max.
2 B1 input Gate 1, input B. LSTTL-compatible CMOS logic input; V_IH >= 2.0 V, V_IL <= 0.8 V at V_CC = 4.5-5.5 V.
3 Y1 output Gate 1 output, Y1 = A1 AND B1. CMOS push-pull output; V_OH >= V_CC - 0.1 V (light load) or 3.98 V min at I_out = 4.0 mA; V_OL <= 0.26 V at 4.0 mA (V_CC = 4.5 V).
4 A2 input Gate 2, input A. LSTTL-compatible CMOS logic input.
5 B2 input Gate 2, input B. LSTTL-compatible CMOS logic input.
6 Y2 output Gate 2 output, Y2 = A2 AND B2. CMOS push-pull output.
7 GND power_in Ground / V_SS reference (0 V). All input and output voltages are referenced to this pin.
8 Y3 output Gate 3 output, Y3 = A3 AND B3. CMOS push-pull output.
9 A3 input Gate 3, input A. LSTTL-compatible CMOS logic input.
10 B3 input Gate 3, input B. LSTTL-compatible CMOS logic input.
11 Y4 output Gate 4 output, Y4 = A4 AND B4. CMOS push-pull output.
12 A4 input Gate 4, input A. LSTTL-compatible CMOS logic input.
13 B4 input Gate 4, input B. LSTTL-compatible CMOS logic input.
14 VCC power_in Positive supply rail. Operating range 2.0 V to 6.0 V; absolute max 7.0 V. Bypass with a 100 nF ceramic capacitor close to the pin.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • MC74HCT08ADTR2G
  • MC74HCT08ADTR2GDG
  • MC74HCT08ADTR2GDR2G

CAD (KiCad official)

  • Symbol: MC74HCT08ADTR2G
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: mc74hct08adtr2g-etched.step / mc74hct08adtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hct08adtr2g.step / mc74hct08adtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (6 pp, sha256 6f05af467074dae6, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF