component
TL494BDR2G
Public Made by Adomby adom
onsemi DC-DC Controllers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTL494BDR2G
onsemi · DC-DC Controllers · SOIC-16
TL494BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Error Amp 1 Noninv Input | input | Noninverting input of error amplifier 1, with common-mode range of -0.3 V to VCC-2.0 V. |
| 2 | Error Amp 1 Inv Input | input | Inverting input of error amplifier 1, with common-mode range of -0.3 V to VCC-2.0 V. |
| 3 | Compen/PWM Comp Input | bidirectional | Error amplifier outputs (active high, ORed) and PWM comparator input for compensation/feedback, with the PWM comparator spanning 0.5 V to 3.5 V. |
| 4 | Deadtime Control | input | Deadtime control comparator input, set to a fixed voltage from 0 V to 3.3 V to impose additional deadtime, with input bias current of -2.0 uA typ. |
| 5 | CT | passive | Timing capacitor connection that sets oscillator frequency (fosc ≈ 1.1/(RT·CT)), recommended 0.0047 uF to 10 uF. |
| 6 | RT | passive | Timing resistor connection that sets oscillator frequency, recommended 1.8 kΩ to 500 kΩ. |
| 7 | Ground | power_in | Ground reference for the device. |
| 8 | C1 | passive | Collector of uncommitted output transistor Q1, rated to 500 mA and 42 V maximum. |
| 9 | E1 | passive | Emitter of output transistor Q1, rated to 500 mA source or sink. |
| 10 | E2 | passive | Emitter of output transistor Q2, rated to 500 mA source or sink. |
| 11 | C2 | passive | Collector of uncommitted output transistor Q2, rated to 500 mA and 42 V maximum. |
| 12 | VCC | power_in | Power supply input, 7.0 V to 40 V recommended operating range and 42 V maximum. |
| 13 | Output Control | input | Selects single-ended/parallel operation when grounded or push-pull operation when connected to Vref (2.4 V ≤ VOC ≤ Vref for push-pull per Figure 17 ranges). |
| 14 | Vref Output | power_out | Internal 5.0 V reference output (4.75 V to 5.25 V) capable of sourcing up to 10 mA. |
| 15 | Error Amp 2 Inv Input | input | Inverting input of error amplifier 2, with common-mode range of -0.3 V to VCC-2.0 V. |
| 16 | Error Amp 2 Noninv Input | input | Noninverting input of error amplifier 2, with common-mode range of -0.3 V to VCC-2.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Power Management ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Voltage | VCC | 42 | V | 1 | |||
| Collector Output Voltage | VC1, VC2 | 42 | V | 1 | |||
| Collector Output Current (Each transistor) | IC1, IC2 | 500 | mA | Each transistor (Note 1) | 1 | ||
| Amplifier Input Voltage Range | VIR | -0.3 | 42 | V | 1 | ||
| Power Dissipation | PD | 1000 | mW | TA ≤ 45°C | 1 | ||
| Thermal Resistance, Junction-to-Ambient | RJA | 80 | °C/W | 1 | |||
| Operating Junction Temperature | TJ | 125 | °C | 1 | |||
| Storage Temperature Range | Tstg | -55 | 125 | °C | 1 | ||
| Operating Ambient Temperature Range | TA | -40 | 125 | °C | TL494B variant | 1 | |
| Power Supply Voltage | VCC | 7 | 15 | 40 | V | 2 | |
| Collector Output Voltage | VC1, VC2 | 30 | 40 | V | 2 | ||
| Collector Output Current (Each transistor) | IC1, IC2 | 200 | mA | 2 | |||
| Amplified Input Voltage | Vin | -0.3 | V | Max printed as VCC − 2.0 V | 2 | ||
| Current Into Feedback Terminal | lfb | 0.3 | mA | 2 | |||
| Reference Output Current | lref | 10 | mA | 2 | |||
| Timing Resistor | RT | 1.8 | 30 | 500 | k | 2 | |
| Timing Capacitor | CT | 0.0047 | 0.001 | 10 | F | 2 | |
| Oscillator Frequency | fosc | 1 | 40 | 200 | kHz | 2 | |
| Reference Voltage | Vref | 4.75 | 5 | 5.25 | V | IO = 1.0 mA | 2 |
| Line Regulation | Regline | 2 | 25 | mV | VCC = 7.0 V to 40 V | 2 | |
| Load Regulation | Regload | 3 | 15 | mV | IO = 1.0 mA to 10 mA | 2 | |
| Short Circuit Output Current | ISC | 15 | 35 | 75 | mA | Vref = 0 V | 2 |
| Collector Off-State Current | IC(off) | 2 | 100 | A | VCC = 40 V, VCE = 40 V | 2 | |
| Emitter Off-State Current | IE(off) | -100 | A | VCC = 40 V, VC = 40 V, VE = 0 V | 2 | ||
| Collector-Emitter Saturation Voltage, Common-Emitter | Vsat(C) | 1.1 | 1.3 | V | VE = 0 V, IC = 200 mA | 2 | |
| Collector-Emitter Saturation Voltage, Emitter-Follower | Vsat(E) | 1.5 | 2.5 | V | VC = 15 V, IE = −200 mA | 2 | |
| Output Control Pin Current, Low State | IOCL | 10 | A | VOC ≤ 0.4 V | 2 | ||
| Output Control Pin Current, High State | IOCH | 0.2 | 3.5 | mA | VOC = Vref | 2 | |
| Output Voltage Rise Time, Common-Emitter | tr | 100 | 200 | ns | See Figure 12 | 2 | |
| Output Voltage Rise Time, Emitter-Follower | tr | 100 | 200 | ns | See Figure 13 | 2 | |
| Output Voltage Fall Time, Common-Emitter | tf | 25 | 100 | ns | See Figure 12 | 2 | |
| Output Voltage Fall Time, Emitter-Follower | tf | 40 | 100 | ns | See Figure 13 | 2 | |
| Input Offset Voltage | VIO | 2 | 10 | mV | VO (Pin 3) = 2.5 V | 3 | |
| Input Offset Current | IIO | 5 | 250 | nA | VO (Pin 3) = 2.5 V | 3 | |
| Input Bias Current | IIB | -0.1 | -1 | A | VO (Pin 3) = 2.5 V | 3 | |
| Input Common Mode Voltage Range | VICR | -0.3 | V | VCC = 40 V, TA = 25°C; max printed as VCC−2.0 V | 3 | ||
| Open Loop Voltage Gain | AVOL | 70 | 95 | dB | VO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 k | 3 | |
| Common Mode Rejection Ratio | CMRR | 65 | 90 | dB | VCC = 40 V | 3 | |
| Output Sink Current | IO− | 0.3 | 0.7 | mA | VO (Pin 3) = 0.7 V | 3 | |
| Output Source Current | IO+ | 2 | -4 | mA | VO (Pin 3) = 3.5 V | 3 | |
| Input Threshold Voltage (Zero Duty Cycle) | VTH | 2.5 | 4.5 | V | 3 | ||
| Input Sink Current | II− | 0.3 | 0.7 | mA | V(Pin 3) = 0.7 V | 3 | |
| Input Bias Current (Pin 4) | IIB(DT) | -2 | -10 | A | VPin 4 = 0 V to 5.25 V | 3 | |
| Maximum Duty Cycle, Each Output, Push-Pull Mode | DCmax | 45 | 48 | % | VPin 4 = 0 V, CT = 0.01 F, RT = 12 k | 3 | |
| Maximum Duty Cycle, Each Output, Push-Pull Mode | DCmax | 45 | 50 | 50 | % | VPin 4 = 0 V, CT = 0.001 F, RT = 30 k | 3 |
| Input Threshold Voltage (Pin 4), Zero Duty Cycle | Vth | 2.8 | 3.3 | V | Zero Duty Cycle | 3 | |
| Input Threshold Voltage (Pin 4), Maximum Duty Cycle | Vth | 0 | V | Maximum Duty Cycle | 3 | ||
| Frequency Change with Temperature | fosc(T) | 12 | % | TA = Tlow to Thigh; CT = 0.01 F, RT = 12 k | 3 | ||
| Turn-On Threshold | Vth | 5.5 | 6.43 | 7 | V | VCC increasing, Iref = 1.0 mA | 3 |
| Standby Supply Current | ICC | 5.5 | 10 | mA | Pin 6 at Vref, VCC = 15 V | 3 | |
| Standby Supply Current | ICC | 7 | 15 | mA | Pin 6 at Vref, VCC = 40 V | 3 |
CAD (KiCad official)
- Symbol:
TL494BDR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
tl494bdr2g-etched.step/tl494bdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tl494bdr2g.step/tl494bdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (14 pp, sha256
22e2ba6778253a07, retrieved 2026-11-07, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).