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AD5445YCPZ
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Analog Devices Digital To Analog Converters (DACs), LFCSP-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5445YCPZ
Analog Devices · Digital To Analog Converters (DACs) · LFCSP-20(4x4)
AD5445YCPZ from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin. |
| 2 | DB11 | bidirectional | Parallel data bit 11 (MSB), written to the input latch and readable back from the DAC register. |
| 3 | DB10 | bidirectional | Parallel data bit 10, written to the input latch and readable back from the DAC register. |
| 4 | DB9 | bidirectional | Parallel data bit 9, written to the input latch and readable back from the DAC register. |
| 5 | DB8 | bidirectional | Parallel data bit 8, written to the input latch and readable back from the DAC register. |
| 6 | DB7 | bidirectional | Parallel data bit 7, written to the input latch and readable back from the DAC register. |
| 7 | DB6 | bidirectional | Parallel data bit 6, written to the input latch and readable back from the DAC register. |
| 8 | DB5 | bidirectional | Parallel data bit 5, written to the input latch and readable back from the DAC register. |
| 9 | DB4 | bidirectional | Parallel data bit 4, written to the input latch and readable back from the DAC register. |
| 10 | DB3 | bidirectional | Parallel data bit 3, written to the input latch and readable back from the DAC register. |
| 11 | DB2 | bidirectional | Parallel data bit 2, written to the input latch and readable back from the DAC register. |
| 12 | DB1 | bidirectional | Parallel data bit 1, written to the input latch and readable back from the DAC register. |
| 13 | DB0 | bidirectional | Parallel data bit 0 (LSB), written to the input latch and readable back from the DAC register. |
| 14 | CS | input | Active-low chip select used with R/W to load parallel data to the input latch or read data from the DAC register; the rising edge of CS loads data. |
| 15 | R/W | input | Read/Write: when low, used with CS to load parallel data; when high, used with CS to read back the contents of the DAC register. |
| 16 | VDD | power_in | Positive power supply input, operable from 2.5 V to 5.5 V. |
| 17 | VREF | power_in | DAC reference voltage input terminal (reference input range ±10 V). |
| 18 | RFB | passive | DAC feedback resistor pin that establishes the voltage output by connecting to the external amplifier output. |
| 19 | IOUT1 | output | DAC current output. |
| 20 | IOUT2 | passive | DAC analog ground; must normally be tied to the analog ground of the system. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-20(4x4) |
| Category | Data Converters |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (AD5445) | INL | -1 | 1 | LSB | AD5445 | 3 | |
| Differential Nonlinearity (AD5445) | DNL | -1 | 2 | LSB | Guaranteed monotonic | 3 | |
| Gain Error | -10 | 10 | mV | 3 | |||
| Gain Error Temperature Coefficient | -5 | 5 | ppm FSR/°C | 3 | |||
| Output Leakage Current | -10 | 10 | nA | Data = 0x0000, TA = 25°C, IOUT1 | 3 | ||
| Output Leakage Current | -20 | 20 | nA | Data = 0x0000, T = −40°C to +125°C, IOUT1 | 3 | ||
| Reference Input Range | -10 | 10 | V | 3 | |||
| VREF Input Resistance | 8 | 10 | 12 | kΩ | Input resistance TC = -50 ppm/°C | 3 | |
| RFB Resistance | RFB | 8 | 10 | 12 | kΩ | Input resistance TC = -50 ppm/°C | 3 |
| Input Capacitance, Code Zero Scale | 3 | 6 | pF | Code Zero Scale | 3 | ||
| Input Capacitance, Code Full Scale | 5 | 8 | pF | Code Full Scale | 3 | ||
| Input High Voltage | VIH | 1.7 | V | 3 | |||
| Input Low Voltage | VIL | 0.6 | V | 3 | |||
| Output Low Voltage | VOL | 0.4 | V | VDD = 4.5 V to 5 V, ISINK = 200 µA | 3 | ||
| Input Leakage Current | IIL | 1 | µA | 3 | |||
| Digital Input Capacitance | 4 | 10 | pF | 3 | |||
| Output Voltage Settling Time to ±16 mV | 30 | 60 | ns | VREF = ±3.5 V, RLOAD = 100 Ω, measured to ±16 mV of full scale | 3 | ||
| Output Voltage Settling Time to ±4 mV | 35 | 70 | ns | VREF = ±3.5 V, RLOAD = 100 Ω, measured to ±4 mV of full scale | 3 | ||
| Output Voltage Settling Time to ±1 mV | 80 | 120 | ns | VREF = ±3.5 V, RLOAD = 100 Ω, measured to ±1 mV of full scale | 3 | ||
| Digital Delay | 20 | 40 | ns | Interface delay time | 3 | ||
| 10% to 90% Settling Time | 15 | 30 | ns | Rise and fall time, VREF = 10 V, RLOAD = 100 Ω | 3 | ||
| IOUT1 Output Capacitance, all 0s | 12 | 17 | pF | All 0s loaded | 4 | ||
| IOUT1 Output Capacitance, all 1s | 25 | 30 | pF | All 1s loaded | 4 | ||
| IOUT2 Output Capacitance, all 0s | 22 | 25 | pF | All 0s loaded | 4 | ||
| IOUT2 Output Capacitance, all 1s | 10 | 12 | pF | All 1s loaded | 4 | ||
| Power Supply Range | VDD | 2.5 | 5.5 | V | 4 | ||
| Supply Current | IDD | 0.6 | µA | TA = 25°C, logic inputs = 0 V or VDD | 4 | ||
| Supply Current | IDD | 0.4 | 5 | µA | Logic inputs = 0 V or VDD, T= −40°C to +125°C | 4 | |
| R/W to CS setup time | t1 | 0 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| R/W to CS hold time | t2 | 0 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| CS low time (write cycle) | t3 | 10 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| Data setup time | t4 | 6 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| Data hold time | t5 | 0 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| R/W high to CS low | t6 | 5 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| CS min high time | t7 | 9 | ns | VDD = 2.5 V to 5.5 V | 5 | ||
| CS min high time | t7 | 7 | ns | VDD = 4.5 V to 5.5 V | 5 | ||
| Data access time | t8 | 20 | 40 | ns | VDD = 2.5 V to 5.5 V | 5 | |
| Data access time | t8 | 10 | 20 | ns | VDD = 4.5 V to 5.5 V | 5 | |
| Bus relinquish time | t9 | 5 | 10 | ns | VDD = 2.5 V to 5.5 V and 4.5 V to 5.5 V | 5 | |
| VDD to GND | VDD | -0.3 | 7 | V | 6 | ||
| VREF, RFB to GND | -12 | 12 | V | 6 | |||
| IOUT1, IOUT2 to GND | -0.3 | 7 | V | 6 | |||
| Operating Temperature Range (Y Version) | -40 | 125 | °C | Extended Industrial | 6 | ||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Junction Temperature | 150 | °C | 6 | ||||
| Lead Temperature, Soldering | 300 | °C | 10 sec | 6 | |||
| IR Reflow, Peak Temperature | 235 | °C | <20 sec | 6 | |||
| 20-Lead LFCSP θJA Thermal Impedance | θJA | 135 | °C/W | 6 | |||
| Reference Multiplying Bandwidth | 10 | MHz | VREF = ±3.5 V; DAC loaded all 1s | 3 |
CAD (KiCad official)
- Symbol:
AD5445YCPZ - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)
- 3D model files:
ad5445ycpz-etched.step/ad5445ycpz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5445ycpz.step/ad5445ycpz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
8e6ae7a875ffd586, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).