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AT32F435ZGT7

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ARTERY Microcontroller Units (MCUs/MPUs/SOCs), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AT32F435ZGT7

ARTERY · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-144(20x20)

AT32F435ZGT7 from ARTERY, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V tolerant FT GPIO; alternates include TMR3_EXT, SPI4_SCK, I2S4_CK, QSPI1_IO2 and XMC_A23.
2 PE3 bidirectional 5 V tolerant FT GPIO; alternates include TMR3_CH1, TMR20_CH2, XMC_A19 and DVP_D9.
3 PE4 bidirectional 5 V tolerant FT GPIO; alternates include CLKOUT1, TMR3_CH2, SPI4_CS, XMC_A20 and DVP_D4.
4 PE5 bidirectional 5 V tolerant FT GPIO; alternates include TMR3_CH3, TMR9_CH1, SPI4_MISO, XMC_A21 and DVP_D6.
5 PE6 bidirectional 5 V tolerant FT GPIO; alternates include TMR3_CH4, TMR9_CH2, SPI4_MOSI, I2S4_SD and XMC_A22.
6 VBAT power_in Battery supply input 1.62-3.6 V for LEXT, ERTC and the battery-powered registers when VDD is absent.
7 PC13 bidirectional 5 V tolerant FT GPIO in the battery domain; output current is limited to 3 mA by the power switch so it cannot source LEDs; alternates ERTC_AF1 and WKUP2.
8 PC14 / LEXT_IN bidirectional Standard-level TC GPIO limited to 3 mA output by the power switch; also the LEXT 32.768 kHz oscillator input.
9 PC15 / LEXT_OUT bidirectional Standard-level TC GPIO limited to 3 mA output by the power switch; also the LEXT 32.768 kHz oscillator output.
10 PF0 bidirectional 5 V tolerant FT GPIO; alternates I2C2_SDA and XMC_A0.
11 PF1 bidirectional 5 V tolerant FT GPIO; alternates I2C2_SCL and XMC_A1.
12 PF2 bidirectional 5 V tolerant FT GPIO; alternates TMR20_CH3, I2C2_SMBA and XMC_A2.
13 PF3 bidirectional FTa GPIO; 5 V tolerant only in input modes and must stay below VDD+0.3 V in analog mode; ADC3_IN9 analog input.
14 PF4 bidirectional FTa GPIO; 5 V tolerant only in input modes and must stay below VDD+0.3 V in analog mode; ADC3_IN14 analog input.
15 PF5 bidirectional FTa GPIO; 5 V tolerant only in input modes and must stay below VDD+0.3 V in analog mode; ADC3_IN15 analog input.
16 VSS power_in Digital ground.
17 VDD power_in Digital supply 2.6-3.6 V.
18 PF6 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC3_IN4 analog input; alternates TMR10_CH1, UART7_RX, QSPI1_IO3 and XMC_NIORD.
19 PF7 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC3_IN5 analog input; alternates TMR11_CH1, UART7_TX, QSPI1_IO2 and XMC_NREG.
20 PF8 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC3_IN6 analog input; alternates TMR13_CH1, QSPI1_IO0 and XMC_NIOWR.
21 PF9 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC3_IN7 analog input; alternates TMR14_CH1, TMR20_BRK, QSPI1_IO1 and XMC_CD.
22 PF10 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC3_IN8 analog input; alternates TMR1_EXT, TMR5_CH4, QSPI1_SCK, XMC_INTR and DVP_D11.
23 PH0 / HEXT_IN bidirectional Standard-level TC GPIO; also the HEXT 4-25 MHz crystal oscillator input; alternate I2C1_SDA.
24 PH1 / HEXT_OUT bidirectional Standard-level TC GPIO; also the HEXT 4-25 MHz crystal oscillator output; alternate I2C1_SCL.
25 NRST bidirectional Active-low bidirectional reset pin with internal weak pull-up of 30-50 kΩ; also drives the internal reset output.
26 PC0 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC123_IN10 fast analog channel; alternates I2C3_SCL, UART7_TX, SDIO2_D0 and XMC_SDNWE.
27 PC1 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC123_IN11 fast analog channel; alternates I2C3_SDA, SPI2_MOSI, I2S2_SD, SDIO2_D1 and EMAC_MDC.
28 PC2 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC123_IN12 fast analog channel; alternates TMR20_CH2, SPI2_MISO, SDIO2_D2 and XMC_NWE.
29 PC3 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC123_IN13 fast analog channel; alternates SPI2_MOSI, I2S2_SD, QSPI2_IO1, SDIO2_D3 and XMC_A0.
30 NC unconnected Not connected on the LQFP144 package.
31 VSSA/VREF- power_in Analog ground and negative ADC/DAC reference voltage; VSSA must be connected to VSS.
32 VREF+ power_in Positive ADC/DAC reference voltage; the DAC reference input is specified at 2.0-3.6 V.
33 VDDA power_in Analog supply 2.6-3.6 V that must be connected to VDD.
34 PA0 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC123_IN0 fast analog channel; alternates TMR2_CH1, I2C2_SCL, USART2_CTS and UART4_TX; also WKUP1.
35 PA1 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC123_IN1 fast analog channel; alternates TMR2_CH2, I2C2_SDA, USART2_RTS_DE, UART4_RX and QSPI1_IO3.
36 PA2 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC123_IN2 analog input; alternates TMR2_CH3, TMR9_CH1, USART2_TX, SDIO2_CK and EMAC_MDIO.
37 PA3 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC123_IN3 analog input; alternates TMR2_CH4, I2S2_MCK, USART2_RX, QSPI2_IO3 and SDIO2_CMD.
38 VSS power_in Digital ground.
39 VDD power_in Digital supply 2.6-3.6 V.
40 PA4 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC12_IN4 analog input and DAC1_OUT; alternates SPI1_CS, I2S3_WS, USART2_CK and SDIO2_D4.
41 PA5 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC12_IN5 analog input and DAC2_OUT; alternates TMR2_CH1, SPI1_SCK, I2S1_CK and SDIO2_D5.
42 PA6 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC12_IN6 analog input; alternates TMR1_BRK, TMR3_CH1, SPI1_MISO, I2S2_MCK and SDIO1_CMD.
43 PA7 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC12_IN7 analog input; alternates TMR1_CH1C, TMR3_CH2, SPI1_MOSI, I2S1_SD and SDIO2_D3.
44 PC4 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC12_IN14 analog input; alternates TMR9_CH1, I2S1_MCK, USART3_TX, QSPI1_IO2 and SDIO2_CK.
45 PC5 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC12_IN15 analog input; alternates TMR9_CH2, I2C1_SMBA, USART3_RX, QSPI1_IO3 and SDIO2_CMD.
46 PB0 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC12_IN8 analog input; alternates TMR1_CH2C, TMR3_CH3, I2S1_MCK, USART2_RX and SDIO1_D1.
47 PB1 bidirectional FTa GPIO; 5 V tolerant only in input modes; ADC12_IN9 analog input; alternates TMR1_CH3C, TMR3_CH4, SPI2_SCK, USART3_RTS_DE and SDIO1_D2.
48 PB2 / BOOT1 bidirectional FT GPIO that also serves as the BOOT1 boot-mode input; alternates TMR2_CH4, TMR20_CH1, I2C3_SMBA, SPI3_MOSI and SDIO1_CK.
49 PF11 bidirectional 5 V tolerant FT GPIO; alternates TMR20_EXT, TMR8_EXT, XMC_SDNRAS and DVP_D12.
50 PF12 bidirectional 5 V tolerant FT GPIO; alternates TMR20_CH1, TMR8_BRK and XMC_A6.
51 VSS power_in Digital ground.
52 VDD power_in Digital supply 2.6-3.6 V.
53 PF13 bidirectional 5 V tolerant FT GPIO; alternates TMR20_CH2, I2C3_SMBA and XMC_A7.
54 PF14 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability; alternates TMR20_CH3, I2C3_SCL and XMC_A8.
55 PF15 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability; alternates TMR20_CH4, I2C3_SDA and XMC_A9.
56 PG0 bidirectional 5 V tolerant FT GPIO; alternates TMR20_CH1C, SPI1_MISO, CAN1_RX and XMC_A10.
57 PG1 bidirectional 5 V tolerant FT GPIO; alternates TMR20_CH2C, SPI1_MOSI, I2S1_SD, CAN1_TX and XMC_A11.
58 PE7 bidirectional 5 V tolerant FT GPIO; alternates TMR1_EXT, UART7_RX, QSPI2_IO0 and XMC_D4.
59 PE8 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH1C, UART4_TX, UART7_TX, QSPI2_IO1 and XMC_D5.
60 PE9 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH1, UART4_RX, QSPI2_IO2 and XMC_D6.
61 VSS power_in Digital ground.
62 VDD power_in Digital supply 2.6-3.6 V.
63 PE10 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH2C, UART5_TX, QSPI2_IO3 and XMC_D7.
64 PE11 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH2, SPI4_CS, I2S4_WS, UART5_RX and XMC_D8.
65 PE12 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH3C, SPI1_CS, I2S1_WS, SPI4_SCK and XMC_D9.
66 PE13 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH3, SPI1_SCK, I2S1_CK, SPI4_MISO and XMC_D10.
67 PE14 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH4, SPI1_MISO, SPI4_MOSI, I2S4_SD and XMC_D11.
68 PE15 bidirectional 5 V tolerant FT GPIO; alternates TMR1_BRK, SPI1_MOSI, I2S1_SD and XMC_D12.
69 PB10 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability; alternates TMR2_CH3, I2C2_SCL, SPI2_SCK, USART3_TX, SDIO1_D7 and XMC_NOE.
70 PB11 bidirectional 5 V tolerant FT GPIO; alternates TMR2_CH4, TMR5_CH4, I2C2_SDA, USART3_RX, QSPI1_IO0 and EMAC_MII_TX_EN.
71 PH3 bidirectional 5 V tolerant FT GPIO; alternates TMR5_CH2, I2C2_SDA, UART4_TX and QSPI1_IO1.
72 VDD power_in Digital supply 2.6-3.6 V.
73 PB12 bidirectional 5 V tolerant FT GPIO; alternates TMR1_BRK, TMR5_CH1, I2C2_SMBA, SPI2_CS, CAN2_RX, OTGFS2_ID and XMC_D13.
74 PB13 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH1C, I2C3_SMBA, SPI2_SCK, I2S2_CK, USART3_CTS, CAN2_TX and OTGFS2_VBUS.
75 PB14 bidirectional Standard-level TC GPIO; alternates TMR1_CH2C, TMR8_CH2C, I2C3_SDA, SPI2_MISO, USART3_RTS_DE, OTGFS2_D-, SDIO1_D6 and XMC_D0.
76 PB15 bidirectional Standard-level TC GPIO; alternates ERTC_REFIN, TMR1_CH3C, TMR8_CH3C, I2C3_SCL, SPI2_MOSI, OTGFS2_D+ and SDIO1_CK.
77 PD8 bidirectional 5 V tolerant FT GPIO; alternates USART3_TX, EMAC_MII_RX_DV and XMC_D13.
78 PD9 bidirectional 5 V tolerant FT GPIO; alternates USART3_RX, EMAC_MII_RXD0 and XMC_D14.
79 PD10 bidirectional 5 V tolerant FT GPIO; alternates USART3_CK, EMAC_MII_RXD1 and XMC_D15.
80 PD11 bidirectional 5 V tolerant FT GPIO; alternates I2C2_SMBA, USART3_CTS, QSPI1_IO0, XMC_A14 and XMC_A16_CLE.
81 PD12 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability; alternates TMR4_CH1, I2C2_SCL, USART3_RTS_DE, QSPI1_IO1 and XMC_A15.
82 PD13 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability; alternates TMR4_CH2, I2C2_SDA, UART8_TX, QSPI1_IO3 and XMC_A18.
83 VSS power_in Digital ground.
84 VDD power_in Digital supply 2.6-3.6 V.
85 PD14 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability; alternates TMR4_CH3, I2C3_SCL, UART8_RX and XMC_D0.
86 PD15 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability; alternates TMR4_CH4, I2C3_SDA and XMC_D1.
87 PG2 bidirectional 5 V tolerant FT GPIO; alternates TMR20_CH3C and XMC_A12.
88 PG3 bidirectional 5 V tolerant FT GPIO; alternates TMR20_BRK and XMC_A13.
89 PG4 bidirectional 5 V tolerant FT GPIO; alternates XMC_A14 and XMC_SDBA0.
90 PG5 bidirectional 5 V tolerant FT GPIO; alternates TMR20_EXT, XMC_A15 and XMC_SDBA1.
91 PG6 bidirectional 5 V tolerant FT GPIO; alternates QSPI1_CS, XMC_INT2 and DVP_D12.
92 PG7 bidirectional 5 V tolerant FT GPIO; alternates USART6_CK, XMC_INT3 and DVP_D13.
93 PG8 bidirectional 5 V tolerant FT GPIO; alternates QSPI2_CS, USART6_RTS_DE, EMAC_PPS_OUT and XMC_SDCLK.
94 VSS power_in Digital ground.
95 VDD power_in Digital supply 2.6-3.6 V.
96 PC6 bidirectional 5 V tolerant FT GPIO; alternates TMR3_CH1, TMR8_CH1, I2C1_SCL, I2S2_MCK, USART6_TX, SDIO1_D6 and DVP_D0.
97 PC7 bidirectional 5 V tolerant FT GPIO; alternates TMR3_CH2, TMR8_CH2, I2C1_SDA, SPI2_SCK, I2S2_CK, USART6_RX and SDIO1_D7.
98 PC8 bidirectional 5 V tolerant FT GPIO; alternates TMR3_CH3, TMR8_CH3, I2S4_MCK, TMR20_CH3, UART8_TX, USART6_CK and SDIO1_D0.
99 PC9 bidirectional 5 V tolerant FT GPIO; alternates CLKOUT2, TMR3_CH4, TMR8_CH4, I2C3_SDA, UART8_RX, OTGFS2_OE and SDIO1_D1.
100 PA8 bidirectional 5 V tolerant FT GPIO; alternates CLKOUT1, TMR1_CH1, I2C3_SCL, USART1_CK, USART2_TX, OTGFS1_SOF and SDIO1_D1.
101 PA9 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH2, I2C3_SMBA, SPI2_SCK, USART1_TX, I2C1_SCL, OTGFS1_VBUS and DVP_D0.
102 PA10 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH3, SPI2_MOSI, I2S2_SD, USART1_RX, I2C1_SDA, OTGFS1_ID and DVP_D1.
103 PA11 bidirectional Standard-level TC GPIO; alternates TMR1_CH4, I2C2_SCL, SPI2_CS, USART1_CTS, USART6_TX, CAN1_RX, OTGFS1_D- and DVP_D2.
104 PA12 bidirectional Standard-level TC GPIO; alternates TMR1_EXT, I2C2_SDA, SPI2_MISO, USART1_RTS_DE, USART6_RX, CAN1_TX, OTGFS1_D+ and DVP_D3.
105 PA13 bidirectional 5 V tolerant FT GPIO that is the JTMS/SWDIO debug pin after reset; alternates IR_OUT, SPI3_MISO and OTGFS1_OE.
106 PH2 bidirectional 5 V tolerant FT GPIO; alternates TMR5_CH1, I2C2_SCL, UART4_RX and QSPI1_IO0.
107 VSS power_in Digital ground.
108 VDD power_in Digital supply 2.6-3.6 V.
109 PA14 bidirectional 5 V tolerant FT GPIO that is the JTCK/SWCLK debug pin after reset; alternates SPI3_MOSI, I2S3_SD and USART2_TX.
110 PA15 bidirectional 5 V tolerant FT GPIO that is the JTDI debug pin after reset; alternates TMR2_CH1, TMR2_EXT, SPI1_CS, I2S1_WS, USART1_TX, USART2_RX and XMC_NE2.
111 PC10 bidirectional 5 V tolerant FT GPIO; alternates TMR5_CH2, SPI3_SCK, I2S3_CK, USART3_TX, UART4_TX, QSPI1_IO1, SDIO1_D2 and DVP_D8.
112 PC11 bidirectional 5 V tolerant FT GPIO; alternates TMR5_CH3, I2S3_SDEXT, SPI3_MISO, USART3_RX, UART4_RX, SDIO1_D3, DVP_D4 and XMC_D2.
113 PC12 bidirectional 5 V tolerant FT GPIO; alternates TMR11_CH1, I2C2_SDA, SPI3_MOSI, I2S3_SD, USART3_CK, UART5_TX, SDIO1_CK, DVP_D9 and XMC_D3.
114 PD0 bidirectional 5 V tolerant FT GPIO; alternates SPI4_MISO, SPI3_MOSI, I2S3_SD, SPI2_CS, CAN1_RX, XMC_A5 and XMC_D2.
115 PD1 bidirectional 5 V tolerant FT GPIO; alternates SPI2_SCK, I2S2_CK, SPI2_CS, CAN1_TX, XMC_A6 and XMC_D3.
116 PD2 bidirectional 5 V tolerant FT GPIO; alternates TMR3_EXT, USART3_RTS_DE, UART5_RX, XMC_A7, SDIO1_CMD, DVP_D11 and XMC_NWE.
117 PD3 bidirectional 5 V tolerant FT GPIO; alternates SPI2_SCK, I2S2_CK, SPI2_MISO, USART2_CTS, QSPI1_SCK, XMC_A8, XMC_CLK and DVP_D5.
118 PD4 bidirectional 5 V tolerant FT GPIO; alternates SPI2_MOSI, I2S2_SD, USART2_RTS_DE, XMC_A9 and XMC_NOE.
119 PD5 bidirectional 5 V tolerant FT GPIO; alternates USART2_TX, XMC_A10 and XMC_NWE.
120 VSS power_in Digital ground.
121 VDD power_in Digital supply 2.6-3.6 V.
122 PD6 bidirectional 5 V tolerant FT GPIO; alternates SPI3_MOSI, I2S3_SD, USART2_RX, XMC_A11, XMC_NWAIT and DVP_D10.
123 PD7 bidirectional 5 V tolerant FT GPIO; alternates USART2_CK, XMC_A12, XMC_NE1 and XMC_NCE2.
124 PG9 bidirectional 5 V tolerant FT GPIO; alternates USART6_RX, QSPI1_IO2, XMC_NE2 and DVP_VSYNC.
125 PG10 bidirectional 5 V tolerant FT GPIO; alternates QSPI2_IO2, XMC_NE3, XMC_NCE4_1 and DVP_D2.
126 PG11 bidirectional 5 V tolerant FT GPIO; alternates QSPI2_IO3, SPI4_SCK, I2S4_CK, CAN2_RX, EMAC_MII_TX_EN and DVP_D3.
127 PG12 bidirectional 5 V tolerant FT GPIO; alternates QSPI2_IO1, SPI4_MISO, USART6_RTS_DE, CAN2_TX and XMC_NE4.
128 PG13 bidirectional 5 V tolerant FT GPIO; alternates QSPI2_SCK, SPI4_MOSI, I2S4_SD, USART6_CTS, EMAC_MII_TXD0 and XMC_A24.
129 PG14 bidirectional 5 V tolerant FT GPIO; alternates QSPI2_IO0, SPI4_CS, I2S4_WS, USART6_TX, QSPI1_IO3, EMAC_MII_TXD1 and XMC_A25.
130 VSS power_in Digital ground.
131 VDD power_in Digital supply 2.6-3.6 V.
132 PG15 bidirectional 5 V tolerant FT GPIO; alternates USART6_CTS, XMC_SDNCAS and DVP_D13.
133 PB3 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability; JTDO/SWO debug pin; alternates TMR2_CH2, I2C2_SDA, SPI1_SCK, SPI3_SCK, USART1_RX and DVP_D4.
134 PB4 bidirectional 5 V tolerant FT GPIO; NJTRST debug pin; alternates TMR3_CH1, I2C3_SDA, SPI1_MISO, SPI3_MISO, UART7_TX, SDIO1_D0 and DVP_D5.
135 PB5 bidirectional 5 V tolerant FT GPIO; alternates TMR3_CH2, I2C1_SMBA, SPI1_MOSI, I2S1_SD, SPI3_MOSI, USART1_CK, UART5_RX, CAN2_RX, XMC_SDCKE1 and SDIO1_D3.
136 PB6 bidirectional 5 V tolerant FT GPIO; alternates TMR4_CH1, I2C1_SCL, I2S1_MCK, SPI4_CS, USART1_TX, UART5_TX, CAN2_TX, QSPI1_CS, XMC_SDCS1 and SDIO1_D0.
137 PB7 bidirectional 5 V tolerant FT GPIO; alternates TMR4_CH2, TMR8_BRK, I2C1_SDA, SPI4_SCK, USART1_RX, QSPI2_IO1, XMC_NADV and DVP_VSYNC.
138 BOOT0 input Dedicated boot-mode pin with an internal weak pull-down that cannot be disabled.
139 PB8 bidirectional 5 V tolerant FT GPIO; alternates TMR2_CH1, TMR2_EXT, TMR4_CH3, TMR10_CH1, I2C1_SCL, SPI4_MISO, UART5_RX, CAN1_RX, QSPI2_CS, SDIO1_D4 and DVP_D6.
140 PB9 bidirectional 5 V tolerant FTf GPIO with 20 mA sink capability; alternates IR_OUT, TMR2_CH2, TMR4_CH4, TMR11_CH1, I2C1_SDA, SPI2_CS, CAN1_TX, QSPI1_CS, SDIO1_D5 and DVP_D7.
141 PE0 bidirectional 5 V tolerant FT GPIO; alternates TMR4_EXT, TMR20_EXT, UART8_RX, XMC_LB, XMC_SDDQML and DVP_D2.
142 PE1 bidirectional 5 V tolerant FT GPIO; alternates TMR1_CH2C, TMR20_CH4, UART8_TX, XMC_UB, XMC_SDDQMH and DVP_D3.
143 VSS power_in Digital ground.
144 VDD power_in Digital supply 2.6-3.6 V.

Key specifications

Parameter Value
Manufacturer ARTERY
Package LQFP-144(20x20)
Category Single Chip Microcomputer/Microcontroller
Pins 144

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (VDDx-VSS) VDDx-VSS -0.3 4 V 47
Input voltage on FTa pin, input floating/pull-up/pull-down mode VIN 6 V 在FTa引脚上的输入电压，引脚设置为输入浮空、输入上拉、或输入下拉模式; min VSS-0.3 47
Input voltage on TC pin VIN 4 V 在TC引脚上的输入电压; min VSS-0.3 47
Voltage difference between different supply pins /ΔVDDx/ 50 mV 不同供电引脚之间的电压差 47
Voltage difference between different ground pins /VSSx-VSS/ 50 mV 不同接地引脚之间的电压差 47
Total current into VDD/VDDA supply pins IVDD 250 mA 外部主供电电压（包含VDDA和VDD） 47
Total current out of VSS ground line IVSS 250 mA 经过VSS地线的总电流（流出电流） 47
Output sink current on any GPIO and control pin IIO 25 mA 任意GPIO和控制引脚上的输出灌电流 47
Output current on any GPIO and control pin IIO -25 mA 任意GPIO和控制引脚上的输出电流 47
Storage temperature range TSTG -60 150 °C 47
Maximum junction temperature TJ 125 °C 47
Data transfer mode clock frequency fPP 0 48 MHz 94
Clock low time tW(CKL) 32 ns 94
Clock high time tW(CKH) 30 ns 94
Clock rise time tr 4 ns 94
Clock fall time tf 5 ns 94
Clock setup time (CMD, D input) tISU 2 ns 94
Clock hold time (CMD, D input) tIH 0 ns 94
Output valid time, MMC and SD high-speed mode tOV 6 ns 94
Output hold time, MMC and SD high-speed mode tOH 0 ns 94
Output valid default time, SD default mode tOVD 7 ns 94
Output hold default time, SD default mode tOHD 0.5 ns 94
OTGFS transceiver startup time tSTARTUP 1 μs 95
OTGFS operating voltage VDD 3 3.6 V 95
Differential input sensitivity VDI 0.2 V I(OTGFS_D+/D-) 95
Static output low level VOL 0.3 V 1.24 kΩ的RL接至3.6 V 95
Static output high level VOH 2.8 3.6 V 15 kΩ的RL接至VSS 95
OTGFS_D+ internal pull-up resistor RPU 0.97 1.24 1.58 kΩ VIN = VSS 95
OTGFS_D+/D- internal pull-down resistor RPD 15 19 25 kΩ VIN = VDD 95
Rise time (10% to 90%) tr 4 20 ns CL ≤ 50 pF 95
Fall time (10% to 90%) tf 4 20 ns CL ≤ 50 pF 95
Rise/fall time matching tr/tf trfm 90 110 % 95
Output signal crossover voltage VCRS 1.3 2 V 95
Ethernet operating voltage VDD 3 3.6 V 96
MDC period tMDC 509 510 511 ns 1.96 MHz，fAHB = 200 MHz 96
MDIO write data valid time td(MDIO) 13.5 14.5 15.5 ns 96
MDIO read data setup time tsu(MDIO) 35 ns 96
MDIO read data hold time th(MDIO) 0 ns 96
RXD receive data setup time tsu(RXD) 4 ns 96
RXD receive data hold time tih(RXD) 2 ns 96
Carrier setup time tsu(DV) 4 ns 96
Carrier hold time tih(DV) 2 ns 96
Transmit enable valid delay td(TXEN) 8 10 16 ns 96
Transmit data valid delay td(TXD) 7 10 16 ns 96
Supply voltage range VDD 2.6 3.6 V 2.6至3.6 V供电 (features summary) 1
Operating temperature range -40 105 °C 温度范围：-40至+105 °C 1
HICK frequency accuracy at 25 °C -1 1 % 25 °C 48 MHz HICK 达1 %精度 1
HICK frequency accuracy from -40 °C to +105 °C -2.5 2.5 % -40 °C至+105 °C 达2.5 %精度 1

CAD (KiCad official)

  • Symbol: AT32F435ZGT7
  • Footprint: Package_QFP:LQFP-144_20x20mm_P0.5mm
  • 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: at32f435zgt7-etched.step / at32f435zgt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); at32f435zgt7.step / at32f435zgt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: ARTERY datasheet (118 pp, sha256 1dc0c659f12e7670, retrieved 2026-10-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF