ZGAD250D14 from Zynalog, in a QFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; pins 1, 2 and 64 may share one bypass capacitor.
2	VDD	power_in	1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 1 and 64.
3	GND	power_in	Power ground; the exposed pad on the package underside must be soldered to the PCB ground.
4	VinA+	input	Channel A differential analog input positive; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase.
5	VinA-	input	Channel A differential analog input negative; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase.
6	GND	power_in	Power ground; the exposed pad on the package underside must be soldered to the PCB ground.
7	SENSE	input	External reference input; connecting it to VDD selects the internal reference with a +/-0.75V input range, while an external reference of 1.2V to 1.3V gives a +/-0.6*VSENSE input range.
8	VREF	power_in	Reference voltage output, nominally 1.25V, bypassed to ground with a 2.2uF ceramic capacitor.
9	GND	power_in	Power ground; the exposed pad on the package underside must be soldered to the PCB ground.
10	VCM	output	Common-mode bias output, nominally 0.435*VDD, used to set the common-mode bias of the analog inputs and bypassed to ground with a 0.1uF ceramic capacitor.
11	GND	power_in	Power ground; the exposed pad on the package underside must be soldered to the PCB ground.
12	VinB-	input	Channel B differential analog input negative; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase.
13	VinB+	input	Channel B differential analog input positive; the differential input voltage should be kept within 1.5V and the two inputs should be 180 degrees out of phase.
14	GND	power_in	Power ground; the exposed pad on the package underside must be soldered to the PCB ground.
15	VDD	power_in	1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; pins 15, 16 and 17 may share one bypass capacitor.
16	VDD	power_in	1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 15 and 17.
17	VDD	power_in	1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 15 and 16.
18	GND	power_in	Power ground; the exposed pad on the package underside must be soldered to the PCB ground.
19	CLK+	input	Differential clock input positive; conversion starts on the rising edge of the clock.
20	CLK-	input	Differential clock input negative; conversion starts on the falling edge of the clock.
21	GND	power_in	Power ground; the exposed pad on the package underside must be soldered to the PCB ground.
22	OF-	output	Overflow/underflow LVDS output, negative leg; OF+ is high when an overflow or underflow occurs, and channel A and B overflow flags are multiplexed onto this pair.
23	OF+	output	Overflow/underflow LVDS output, positive leg; high when an overflow or underflow occurs, and channel A and B overflow flags are multiplexed onto this pair.
24	DB0_1-	output	Channel B DDR LVDS output negative leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high.
25	DB0_1+	output	Channel B DDR LVDS output positive leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high.
26	DB2_3-	output	Channel B DDR LVDS output negative leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high.
27	DB2_3+	output	Channel B DDR LVDS output positive leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high.
28	DB4_5-	output	Channel B DDR LVDS output negative leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high.
29	DB4_5+	output	Channel B DDR LVDS output positive leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high.
30	DB6_7-	output	Channel B DDR LVDS output negative leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high.
31	DB6_7+	output	Channel B DDR LVDS output positive leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high.
32	DVDD	power_in	1.8V supply for the digital output drivers, bypassed to ground with a separate 0.1uF ceramic capacitor per pin.
33	DGND	power_in	Ground for the digital output drivers.
34	DB8_9-	output	Channel B DDR LVDS output negative leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high.
35	DB8_9+	output	Channel B DDR LVDS output positive leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high.
36	DB10_11-	output	Channel B DDR LVDS output negative leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high.
37	DB10_11+	output	Channel B DDR LVDS output positive leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high.
38	DB12_13-	output	Channel B DDR LVDS output negative leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high.
39	DB12_13+	output	Channel B DDR LVDS output positive leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high.
40	CLKOUT-	output	Data output clock LVDS negative leg, which normally transitions together with the data outputs; its phase can be delayed relative to the data through the timing register.
41	CLKOUT+	output	Data output clock LVDS positive leg, which normally transitions together with the data outputs; its phase can be delayed relative to the data through the timing register.
42	DA0_1-	output	Channel A DDR LVDS output negative leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high.
43	DA0_1+	output	Channel A DDR LVDS output positive leg carrying bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high.
44	DA2_3-	output	Channel A DDR LVDS output negative leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high.
45	DA2_3+	output	Channel A DDR LVDS output positive leg carrying bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high.
46	DA4_5-	output	Channel A DDR LVDS output negative leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high.
47	DA4_5+	output	Channel A DDR LVDS output positive leg carrying bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high.
48	DGND	power_in	Ground for the digital output drivers.
49	DVDD	power_in	1.8V supply for the digital output drivers, bypassed to ground with a separate 0.1uF ceramic capacitor per pin.
50	DA6_7-	output	Channel A DDR LVDS output negative leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high.
51	DA6_7+	output	Channel A DDR LVDS output positive leg carrying bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high.
52	DA8_9-	output	Channel A DDR LVDS output negative leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high.
53	DA8_9+	output	Channel A DDR LVDS output positive leg carrying bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high.
54	DA10_11-	output	Channel A DDR LVDS output negative leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high.
55	DA10_11+	output	Channel A DDR LVDS output positive leg carrying bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high.
56	DA12_13-	output	Channel A DDR LVDS output negative leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high.
57	DA12_13+	output	Channel A DDR LVDS output positive leg carrying bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high.
58	GND	power_in	Power ground; the exposed pad on the package underside must be soldered to the PCB ground.
59	SPI_MISO	output	SPI data readback output in serial mode (MODE=0), open-drain and requiring a 2K pull-up to the 1.8V to 3.3V SPI supply when registers are read back; no function in parallel mode.
60	SPI_MOSI	input	SPI data input in serial mode (MODE=0); in parallel mode (MODE=VDD) it selects LVDS output current, 3.5mA when low and 1.75mA when high at 1.8V to 3.3V logic levels.
61	SPI_SCLK	input	SPI clock input in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables sleep mode when high at 1.8V to 3.3V logic levels.
62	SPI_CS	input	SPI chip select in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables the clock duty cycle stabilizer when high at 1.8V to 3.3V logic levels.
63	MODE	input	Serial/parallel interface mode select; connect directly to GND for SPI mode or to VDD for parallel GPIO mode and do not drive it with a logic signal.
64	VDD	power_in	1.8V analog supply, bypassed to ground with 0.1uF ceramic capacitor; may share the bypass capacitor with pins 1 and 2.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Zynalog
Package	QFN-64(9x9)
Category	ADC/DAC/Data Conversion
Pins	65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog supply voltage	VDD	1.7	1.8	1.9	V		4
Digital supply voltage	DVDD	1.7	1.8	1.9	V		4
Analog supply input current	I_VDD		280	290	mA		4
Digital supply input current	I_DVDD			64	mA		4
Power dissipation, LVDS output 1.75mA, both channels on	P_1.75			580	mW	1.75mA LVDS output, both channels on	4
Power dissipation, LVDS output 3.5mA, both channels on	P_3.5			620	mW	3.5mA LVDS output, both channels on	4
Power dissipation, sleep mode	P_sleep			0.65	mW	睡眠模式	4
Integral nonlinearity	INL	-2	1	2	LSB		4
Differential nonlinearity	DNL	-0.6	0.35	0.6	LSB		4
Offset error		-13	5	13	mV		4
Gain error		-4	1	2.2	%FS		4
LVDS differential output voltage, 3.5mA mode	V_OD	247	350	454	mV	3.5mA模式下	4
LVDS differential output voltage, 1.75mA mode	V_OD	125	175	250	mV	1.75mA模式下	4
LVDS output common-mode voltage	V_OS	1.125	1.25	1.375	V		4
Clock input to clock output delay	tC	1.3	1.6	2	ns	VDD=1.8V, DVDD=1.8V, fS=250MHz	10
Clock input to data output delay	tD	1.7	2	2.3	ns	VDD=1.8V, DVDD=1.8V, fS=250MHz	10
Clock output to data output skew (tC - tD)	tSKEW	0.3	0.4	0.55	ns	VDD=1.8V, DVDD=1.8V, fS=250MHz	10
Maximum input voltage range, VDD and DVDD	VDD,DVDD	-0.3		2	V		6
Maximum analog input voltage range	Analog Vin	-0.3			V	max printed as VDD+0.2	6
Maximum input voltage range, CLK and SENSE	CLK,SENSE	-0.3			V	max printed as VDD+0.2	6
Maximum SPI/GPIO digital voltage range	SPI			3.9	V	min printed as VDD	6
Maximum LVDS output digital voltage range	Data Output	-0.3			V	max printed as DVDD+0.2	6
Working temperature		-40		85	°C		6
Storage temperature		-65		150	°C		6
Power dissipation, low power mode	P_lowpower		180		mW	低功耗模式	4
Signal-to-noise ratio	SNR		70		dB		4
Spurious-free dynamic range	SFDR		90		dB		4

CAD (KiCad official)

Symbol: ZGAD250D14
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: QFN-64(9x9) (KiCad packages3D, STEP)
3D model files: zgad250d14-etched.step / zgad250d14-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zgad250d14.step / zgad250d14.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Zynalog datasheet (19 pp, sha256 60a81de455573fc7, retrieved 2026-11-02, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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ZGAD250D14

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