component
STM32U575ZIT6Q
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownSTM32U575ZIT6Q
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)
STM32U575ZIT6Q from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | FT_ha I/O; alternates TRACECLK, TIM3_ETR, SAI1_CK1, TSC_G7_IO1, LPGPIO1_P14, FMC_A23, SAI1_MCLK_A, EVENTOUT. |
| 2 | PE3 | bidirectional | FT_hat I/O; alternates TRACED0, TIM3_CH1, OCTOSPIM_P1_DQS, TSC_G7_IO2, LPGPIO1_P15, FMC_A19, SAI1_SD_B; additional TAMP_IN6/TAMP_OUT3. |
| 3 | PE4 | bidirectional | FT_hat I/O; alternates TRACED1, TIM3_CH2, SAI1_D2, MDF1_SDI3, TSC_G7_IO3, DCMI_D4/PSSI_D4, FMC_A20, SAI1_FS_A; additional WKUP1, TAMP_IN7/TAMP_OUT8. |
| 4 | PE5 | bidirectional | FT_hat I/O; alternates TRACED2, TIM3_CH3, SAI1_CK2, MDF1_CKI3, TSC_G7_IO4, DCMI_D6/PSSI_D6, FMC_A21, SAI1_SCK_A; additional WKUP2, TAMP_IN8/TAMP_OUT7. |
| 5 | PE6 | bidirectional | FT_ht I/O; alternates TRACED3, TIM3_CH4, SAI1_D1, DCMI_D7/PSSI_D7, FMC_A22, SAI1_SD_A; additional WKUP3, TAMP_IN3/TAMP_OUT6. |
| 6 | VBAT | power_in | Backup domain supply (RTC, backup registers, backup SRAM) for VBAT mode; absolute maximum -0.3 to 4.0 V. |
| 7 | PC13 | bidirectional | FT I/O supplied via VSW power switch; output limited to 2 MHz, 30 pF, 3 mA source; additional WKUP2, RTC_TS/RTC_OUT1, TAMP_IN1/TAMP_OUT2. |
| 8 | PC14-OSC32_IN | bidirectional | FT_o I/O supplied via VSW (output limited to 2 MHz, 30 pF); LSE oscillator input OSC32_IN. |
| 9 | PC15-OSC32_OUT | bidirectional | FT_o I/O supplied via VSW (output limited to 2 MHz, 30 pF); LSE oscillator output OSC32_OUT. |
| 10 | PF0 | bidirectional | FT_fh I/O (Fm+); alternates I2C2_SDA, OCTOSPIM_P2_IO0, FMC_A0, EVENTOUT. |
| 11 | PF1 | bidirectional | FT_fh I/O (Fm+); alternates I2C2_SCL, OCTOSPIM_P2_IO1, FMC_A1, EVENTOUT. |
| 12 | PF2 | bidirectional | FT_h I/O; alternates LPTIM3_CH2, I2C2_SMBA, OCTOSPIM_P2_IO2, FMC_A2; additional WKUP8. |
| 13 | PF3 | bidirectional | FT_h I/O; alternates LPTIM3_IN1, OCTOSPIM_P2_IO3, FMC_A3, EVENTOUT. |
| 14 | PF4 | bidirectional | FT_hv I/O; alternates LPTIM3_ETR, OCTOSPIM_P2_CLK, FMC_A4, EVENTOUT. |
| 15 | PF5 | bidirectional | FT_hv I/O; alternates LPTIM3_CH1, OCTOSPIM_P2_NCLK, FMC_A5, EVENTOUT. |
| 16 | VSS | power_in | Digital ground. |
| 17 | VDD | power_in | Digital supply, 1.71 V to 3.6 V operating; decouple with 100 nF per pin plus 4.7 µF. |
| 18 | PF6 | bidirectional | FT_h I/O; alternates TIM5_ETR, TIM5_CH1, DCMI_D12/PSSI_D12, OCTOSPIM_P2_NCS, OCTOSPIM_P1_IO3, SAI1_SD_B. |
| 19 | PF7 | bidirectional | FT_h I/O; alternates TIM5_CH2, FDCAN1_RX, OCTOSPIM_P1_IO2, SAI1_MCLK_B. |
| 20 | PF8 | bidirectional | FT_h I/O; alternates TIM5_CH3, PSSI_D14, FDCAN1_TX, OCTOSPIM_P1_IO0, SAI1_SCK_B. |
| 21 | PF9 | bidirectional | FT_h I/O; alternates TIM5_CH4, PSSI_D15, OCTOSPIM_P1_IO1, SAI1_FS_B, TIM15_CH1. |
| 22 | PF10 | bidirectional | FT_hv I/O; alternates OCTOSPIM_P1_CLK, PSSI_D15, MDF1_CCK1, DCMI_D11/PSSI_D11, SAI1_D3, TIM15_CH2. |
| 23 | PH0-OSC_IN | bidirectional | FT I/O; HSE oscillator input OSC_IN, EVENTOUT alternate. |
| 24 | PH1-OSC_OUT | bidirectional | FT I/O; HSE oscillator output OSC_OUT, EVENTOUT alternate. |
| 25 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor (RST structure). |
| 26 | PC0 | bidirectional | FT_fha I/O; alternates LPTIM1_IN1, OCTOSPIM_P1_IO7, I2C3_SCL, SPI2_RDY, LPUART1_RX, SDMMC1_D5; analog ADC1_IN1, ADC4_IN1. |
| 27 | PC1 | bidirectional | FT_fhav I/O; alternates TRACED0, LPTIM1_CH1, SPI2_MOSI, I2C3_SDA, LPUART1_TX, SDMMC2_CK, SAI1_SD_A; analog ADC1_IN2, ADC4_IN2. |
| 28 | PC2 | bidirectional | FT_ha I/O; alternates LPTIM1_IN2, SPI2_MISO, MDF1_CCK1, OCTOSPIM_P1_IO5, LPGPIO1_P5; analog ADC1_IN3, ADC4_IN3. |
| 29 | PC3 | bidirectional | FT_ha I/O; alternates LPTIM1_ETR, LPTIM3_CH1, SAI1_D1, SPI2_MOSI, OCTOSPIM_P1_IO6, SAI1_SD_A; analog ADC1_IN4, ADC4_IN4. |
| 30 | VSSA | power_in | Analog ground. |
| 31 | VREF+ | power_in | Voltage reference input / VREFBUF output (VREFBUF_OUT); VREF+ may exceed VDDA by at most 0.4 V. |
| 32 | VDDA | power_in | Analog supply for ADCs, DACs, OPAMPs, COMPs and VREFBUF; decouple with 100 nF + 1 µF. |
| 33 | PA0 | bidirectional | FT_hat I/O; alternates TIM2_CH1, TIM5_CH1, TIM8_ETR, SPI3_RDY, USART2_CTS, UART4_TX, SDMMC2_CMD; additional OPAMP1_VINP, ADC1_IN5, WKUP1, TAMP_IN2/TAMP_OUT1. |
| 34 | PA1 | bidirectional | FT_hat I/O; alternates LPTIM1_CH2, TIM2_CH2, TIM5_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, UART4_RX; additional OPAMP1_VINM, ADC1_IN6, WKUP3, TAMP_IN5/TAMP_OUT4. |
| 35 | PA2 | bidirectional | FT_ha I/O; alternates TIM2_CH3, TIM5_CH3, SPI1_RDY, USART2_TX(boot), LPUART1_TX, UCPD1_FRSTX1; additional COMP1_INP3, ADC1_IN7, WKUP4/LSCO. |
| 36 | PA3 | bidirectional | TT_hav I/O; alternates TIM2_CH4, TIM5_CH4, SAI1_CK1, USART2_RX(boot), LPUART1_RX, OCTOSPIM_P1_CLK; additional OPAMP1_VOUT, ADC1_IN8, WKUP5. |
| 37 | VSS | power_in | Digital ground. |
| 38 | VDD | power_in | Digital supply, 1.71 V to 3.6 V operating. |
| 39 | PA4 | bidirectional | TT_ha I/O; alternates OCTOSPIM_P1_NCS, SPI1_NSS(boot), SPI3_NSS, USART2_CK, DCMI_HSYNC/PSSI_DE; additional ADC1_IN9, ADC4_IN9, DAC1_OUT1, WKUP2. |
| 40 | PA5 | bidirectional | TT_a I/O; alternates CSLEEP, TIM2_CH1/ETR, TIM8_CH1N, PSSI_D14, SPI1_SCK(boot), USART3_RX; additional ADC1_IN10, ADC4_IN10, DAC1_OUT2, WKUP6. |
| 41 | PA6 | bidirectional | FT_ha I/O; alternates CDSTOP, TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO(boot), USART3_CTS, LPUART1_CTS; additional OPAMP2_VINP, ADC1_IN11, ADC4_IN11, WKUP7. |
| 42 | PA7 | bidirectional | FT_fha I/O; alternates SRDSTOP, TIM1_CH1N, TIM3_CH2, TIM8_CH1N, I2C3_SCL, SPI1_MOSI(boot), USART3_TX; additional OPAMP2_VINM, ADC1_IN12, ADC4_IN20, WKUP8. |
| 43 | PB0 | bidirectional | TT_ha I/O; alternates TIM1_CH2N, TIM3_CH3, TIM8_CH2N, LPTIM3_CH1, SPI1_NSS, USART3_CK, COMP1_OUT; additional OPAMP2_VOUT, ADC1_IN15, ADC4_IN18. |
| 44 | PB1 | bidirectional | FT_ha I/O; alternates TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LPTIM3_CH2, MDF1_SDI0, USART3_RTS_DE; additional COMP1_INM1, ADC1_IN16, ADC4_IN19, WKUP4. |
| 45 | PB2 | bidirectional | FT_hat I/O; alternates LPTIM1_CH1, TIM8_CH4N, I2C3_SMBA, SPI1_RDY, MDF1_CKI0, UCPD1_FRSTX1; additional COMP1_INP2, ADC1_IN17, WKUP1, RTC_OUT2. |
| 46 | PF11 | bidirectional | FT_hv I/O; alternates OCTOSPIM_P1_NCLK, DCMI_D12/PSSI_D12, LPTIM4_IN1. |
| 47 | PF12 | bidirectional | FT_h I/O; alternates OCTOSPIM_P2_DQS, FMC_A6, LPTIM4_ETR. |
| 48 | VSS | power_in | Digital ground. |
| 49 | VDD | power_in | Digital supply, 1.71 V to 3.6 V operating. |
| 50 | PF13 | bidirectional | FT_h I/O; alternates I2C4_SMBA, UCPD1_FRSTX2, FMC_A7, LPTIM4_OUT. |
| 51 | PF14 | bidirectional | FT_fha I/O; alternates I2C4_SCL, TSC_G8_IO1, FMC_A8; additional ADC4_IN5. |
| 52 | PF15 | bidirectional | FT_fha I/O; alternates I2C4_SDA, TSC_G8_IO2, FMC_A9; additional ADC4_IN6. |
| 53 | PG0 | bidirectional | FT_ha I/O; alternates OCTOSPIM_P2_IO4, TSC_G8_IO3, FMC_A10; additional ADC4_IN7. |
| 54 | PG1 | bidirectional | FT_ha I/O; alternates OCTOSPIM_P2_IO5, TSC_G8_IO4, FMC_A11; additional ADC4_IN8. |
| 55 | PE7 | bidirectional | FT_h I/O; alternates TIM1_ETR, MDF1_SDI2, FMC_D4, SAI1_SD_B; additional WKUP6. |
| 56 | PE8 | bidirectional | FT_h I/O; alternates TIM1_CH1N, MDF1_CKI2, FMC_D5, SAI1_SCK_B; additional WKUP7. |
| 57 | PE9 | bidirectional | FT_hv I/O; alternates TIM1_CH1, ADF1_CCK0, MDF1_CCK0, OCTOSPIM_P1_NCLK, FMC_D6, SAI1_FS_B. |
| 58 | VSS | power_in | Digital ground. |
| 59 | VDD | power_in | Digital supply, 1.71 V to 3.6 V operating. |
| 60 | PE10 | bidirectional | FT_hav I/O; alternates TIM1_CH2N, ADF1_SDI0, MDF1_SDI4, TSC_G5_IO1, OCTOSPIM_P1_CLK, FMC_D7, SAI1_MCLK_B. |
| 61 | PE11 | bidirectional | FT_ha I/O; alternates TIM1_CH2, SPI1_RDY, MDF1_CKI4, TSC_G5_IO2, OCTOSPIM_P1_NCS, FMC_D8. |
| 62 | PE12 | bidirectional | FT_ha I/O; alternates TIM1_CH3N, SPI1_NSS, MDF1_SDI5, TSC_G5_IO3, OCTOSPIM_P1_IO0, FMC_D9. |
| 63 | PE13 | bidirectional | FT_ha I/O; alternates TIM1_CH3, SPI1_SCK, MDF1_CKI5, TSC_G5_IO4, OCTOSPIM_P1_IO1, FMC_D10. |
| 64 | PE14 | bidirectional | FT_h I/O; alternates TIM1_CH4, TIM1_BKIN2, SPI1_MISO, OCTOSPIM_P1_IO2, FMC_D11. |
| 65 | PE15 | bidirectional | FT_h I/O; alternates TIM1_BKIN, TIM1_CH4N, SPI1_MOSI, OCTOSPIM_P1_IO3, FMC_D12. |
| 66 | PB10 | bidirectional | FT_fhv I/O; alternates TIM2_CH3, LPTIM3_CH1, I2C4_SCL, I2C2_SCL(boot), SPI2_SCK, USART3_TX, LPUART1_RX, COMP1_OUT; additional WKUP8. |
| 67 | PB11 | bidirectional | FT_fh I/O; alternates TIM2_CH4, I2C4_SDA, I2C2_SDA(boot), SPI2_RDY, USART3_RX, LPUART1_TX, COMP2_OUT. |
| 68 | VLXSMPS | power_out | SMPS step-down converter switching node; connect 2.2 µH inductor (ISAT > 0.5 A, DCR < 200 mΩ) to VDD11. |
| 69 | VDDSMPS | power_in | SMPS step-down converter supply input; requires 10 µF ±20% capacitor, ESR < 10 mΩ, rated ≥ 10 V. |
| 70 | VSSSMPS | power_in | SMPS step-down converter ground. |
| 71 | VDD11 | power_in | 1.1 V core supply (SMPS output); requires 2 × 2.2 µF ±20%, ESR < 20 mΩ, rated ≥ 10 V. |
| 72 | VSS | power_in | Digital ground. |
| 73 | VDD | power_in | Digital supply, 1.71 V to 3.6 V operating. |
| 74 | PB13 | bidirectional | FT_fa I/O; alternates TIM1_CH1N, LPTIM3_IN1, I2C2_SCL, SPI2_SCK(boot), MDF1_CKI1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SAI2_SCK_A. |
| 75 | PB14 | bidirectional | FT_fda I/O; alternates TIM1_CH2N, LPTIM3_ETR, TIM8_CH2N, I2C2_SDA, SPI2_MISO(boot), MDF1_SDI2, USART3_RTS_DE, SDMMC2_D0; additional UCPD1_DBCC2. |
| 76 | PB15 | bidirectional | FT_c I/O; alternates RTC_REFIN, TIM1_CH3N, LPTIM2_IN2, TIM8_CH3N, SPI2_MOSI(boot), MDF1_CKI2, FMC_NBL1, SDMMC2_D1; additional UCPD1_CC2, WKUP7; UCPD pull-down Rd 5.1 kΩ active after reset. |
| 77 | PD8 | bidirectional | FT_h I/O; alternates USART3_TX, DCMI_HSYNC/PSSI_DE, FMC_D13. |
| 78 | PD9 | bidirectional | FT_h I/O; alternates LPTIM2_IN2, USART3_RX, DCMI_PIXCLK/PSSI_PDCK, FMC_D14, SAI2_MCLK_A, LPTIM3_IN1. |
| 79 | PD10 | bidirectional | FT_ha I/O; alternates LPTIM2_CH2, USART3_CK, TSC_G6_IO1, FMC_D15, SAI2_SCK_A, LPTIM3_ETR. |
| 80 | PD11 | bidirectional | FT_ha I/O; alternates I2C4_SMBA, USART3_CTS, TSC_G6_IO2, FMC_CLE/FMC_A16, SAI2_SD_A, LPTIM2_ETR; additional ADC4_IN15. |
| 81 | PD12 | bidirectional | FT_fha I/O; alternates TIM4_CH1, I2C4_SCL, USART3_RTS_DE, TSC_G6_IO3, FMC_ALE/FMC_A17, SAI2_FS_A, LPTIM2_IN1; additional ADC4_IN16. |
| 82 | PD13 | bidirectional | FT_fha I/O; alternates TIM4_CH2, I2C4_SDA, TSC_G6_IO4, LPGPIO1_P6, FMC_A18, LPTIM4_IN1, LPTIM2_CH1; additional ADC4_IN17. |
| 83 | VSS | power_in | Digital ground. |
| 84 | VDD | power_in | Digital supply, 1.71 V to 3.6 V operating. |
| 85 | PD14 | bidirectional | FT_h I/O; alternates TIM4_CH3, FMC_D0, LPTIM3_CH1. |
| 86 | PD15 | bidirectional | FT_h I/O; alternates TIM4_CH4, FMC_D1, LPTIM3_CH2. |
| 87 | PG2 | bidirectional | FT_hs I/O supplied by VDDIO2; alternates SPI1_SCK, FMC_A12, SAI2_SCK_B. |
| 88 | PG3 | bidirectional | FT_hs I/O supplied by VDDIO2; alternates SPI1_MISO, FMC_A13, SAI2_FS_B. |
| 89 | PG4 | bidirectional | FT_hs I/O supplied by VDDIO2; alternates SPI1_MOSI, FMC_A14, SAI2_MCLK_B. |
| 90 | PG5 | bidirectional | FT_hs I/O supplied by VDDIO2; alternates SPI1_NSS, LPUART1_CTS, FMC_A15, SAI2_SD_B. |
| 91 | PG6 | bidirectional | FT_hs I/O supplied by VDDIO2; alternates OCTOSPIM_P1_DQS, I2C3_SMBA, SPI1_RDY, LPUART1_RTS_DE, UCPD1_FRSTX1. |
| 92 | PG7 | bidirectional | FT_fhs I/O supplied by VDDIO2; alternates SAI1_CK1, I2C3_SCL, OCTOSPIM_P2_DQS, MDF1_CCK0, LPUART1_TX, UCPD1_FRSTX2, FMC_INT, SAI1_MCLK_A. |
| 93 | PG8 | bidirectional | FT_fs I/O supplied by VDDIO2; alternates I2C3_SDA, LPUART1_RX, EVENTOUT. |
| 94 | VSS | power_in | Digital ground. |
| 95 | VDDIO2 | power_in | I/O supply for PG2-PG15 (_s I/Os), 1.08 to 3.6 V range as per scheme; decouple with 100 nF. |
| 96 | PC6 | bidirectional | FT_a I/O; alternates CSLEEP, TIM3_CH1, TIM8_CH1, MDF1_CKI3, SDMMC1_D0DIR, TSC_G4_IO1, DCMI_D0/PSSI_D0, SDMMC2_D6, SDMMC1_D6, SAI2_MCLK_A. |
| 97 | PC7 | bidirectional | FT_a I/O; alternates CDSTOP, TIM3_CH2, TIM8_CH2, MDF1_SDI3, SDMMC1_D123DIR, TSC_G4_IO2, DCMI_D1/PSSI_D1, SDMMC2_D7, SDMMC1_D7, SAI2_MCLK_B. |
| 98 | PC8 | bidirectional | FT_a I/O; alternates SRDSTOP, TIM3_CH3, TIM8_CH3, TSC_G4_IO3, DCMI_D2/PSSI_D2, SDMMC1_D0, LPTIM3_CH1. |
| 99 | PC9 | bidirectional | FT_a I/O; alternates TRACED0, TIM8_BKIN2, TIM3_CH4, TIM8_CH4, DCMI_D3/PSSI_D3, TSC_G4_IO4, OTG_FS_NOE, SDMMC1_D1, LPTIM3_CH2. |
| 100 | PA8 | bidirectional | FT_hv I/O; alternates MCO, TIM1_CH1, SAI1_CK2, SPI1_RDY, USART1_CK, OTG_FS_SOF, TRACECLK, SAI1_SCK_A, LPTIM2_CH1. |
| 101 | PA9 | bidirectional | FT_u I/O supplied by VDDUSB; alternates TIM1_CH2, SPI2_SCK, DCMI_D0/PSSI_D0, USART1_TX(boot), SAI1_FS_A; additional OTG_FS_VBUS. |
| 102 | PA10 | bidirectional | FT_u I/O supplied by VDDUSB; alternates CRS_SYNC, TIM1_CH3, LPTIM2_IN2, SAI1_D1, DCMI_D1/PSSI_D1, USART1_RX(boot), OTG_FS_ID, SAI1_SD_A. |
| 103 | PA11 | bidirectional | FT_u I/O supplied by VDDUSB; alternates TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, FDCAN1_RX, OTG_FS_DM(boot). |
| 104 | PA12 | bidirectional | FT_u I/O supplied by VDDUSB; alternates TIM1_ETR, SPI1_MOSI, OCTOSPIM_P2_NCS, USART1_RTS_DE, FDCAN1_TX, OTG_FS_DP(boot). |
| 105 | PA13 (JTMS/SWDIO) | bidirectional | FT I/O; JTMS/SWDIO after reset with internal pull-up active; alternates IR_OUT, OTG_FS_NOE, SAI1_SD_B. |
| 106 | VDDUSB | power_in | Supply for USB transceiver and FT_u I/Os (PA9-PA12); decouple with 100 nF. |
| 107 | VSS | power_in | Digital ground. |
| 108 | VDD | power_in | Digital supply, 1.71 V to 3.6 V operating. |
| 109 | PA14 (JTCK/SWCLK) | bidirectional | FT I/O; JTCK/SWCLK after reset with internal pull-down active; alternates LPTIM1_CH1, I2C1_SMBA, I2C4_SMBA, OTG_FS_SOF, SAI1_FS_B. |
| 110 | PA15 (JTDI) | bidirectional | FT_c I/O; JTDI after reset with internal pull-up; alternates TIM2_CH1/ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, SAI2_FS_B; additional UCPD1_CC1; UCPD pull-down Rd 5.1 kΩ active after reset. |
| 111 | PC10 | bidirectional | FT_a I/O; alternates TRACED1, LPTIM3_ETR, ADF1_CCK1, SPI3_SCK, USART3_TX(boot), UART4_TX, TSC_G3_IO2, DCMI_D8/PSSI_D8, SDMMC1_D2, SAI2_SCK_B. |
| 112 | PC11 | bidirectional | FT_ha I/O; alternates LPTIM3_IN1, ADF1_SDI0, OCTOSPIM_P1_NCS, SPI3_MISO, USART3_RX(boot), UART4_RX, TSC_G3_IO3, SDMMC1_D3, SAI2_MCLK_B. |
| 113 | PC12 | bidirectional | FT_hav I/O; alternates TRACED3, SPI3_MOSI, USART3_CK, UART5_TX, TSC_G3_IO4, DCMI_D9/PSSI_D9, SDMMC1_CK, SAI2_SD_B. |
| 114 | PD0 | bidirectional | FT_h I/O; alternates TIM8_CH4N, SPI2_NSS, FDCAN1_RX, FMC_D2. |
| 115 | PD1 | bidirectional | FT_h I/O; alternates SPI2_SCK, FDCAN1_TX, FMC_D3. |
| 116 | PD2 | bidirectional | FT I/O; alternates TRACED2, TIM3_ETR, USART3_RTS_DE, UART5_RX, TSC_SYNC, DCMI_D11/PSSI_D11, SDMMC1_CMD, LPTIM4_ETR. |
| 117 | PD3 | bidirectional | FT_hv I/O; alternates SPI2_SCK, DCMI_D5/PSSI_D5, SPI2_MISO, MDF1_SDI0, USART2_CTS, OCTOSPIM_P2_NCS, FMC_CLK. |
| 118 | PD4 | bidirectional | FT_h I/O; alternates SPI2_MOSI, MDF1_CKI0, USART2_RTS_DE, OCTOSPIM_P1_IO4, FMC_NOE. |
| 119 | PD5 | bidirectional | FT_h I/O; alternates SPI2_RDY, USART2_TX, OCTOSPIM_P1_IO5, FMC_NWE. |
| 120 | VSS | power_in | Digital ground. |
| 121 | VDD | power_in | Digital supply, 1.71 V to 3.6 V operating. |
| 122 | PD6 | bidirectional | FT_hv I/O; alternates SAI1_D1, DCMI_D10/PSSI_D10, SPI3_MOSI, MDF1_SDI1, USART2_RX, OCTOSPIM_P1_IO6, SDMMC2_CK, FMC_NWAIT, SAI1_SD_A. |
| 123 | PD7 | bidirectional | FT_h I/O; alternates MDF1_CKI1, USART2_CK, OCTOSPIM_P1_IO7, SDMMC2_CMD, FMC_NCE/FMC_NE1, LPTIM4_OUT. |
| 124 | PG9 | bidirectional | FT_hs I/O supplied by VDDIO2; alternates OCTOSPIM_P2_IO6, SPI3_SCK(boot), USART1_TX, FMC_NCE/FMC_NE2, SAI2_SCK_A, TIM15_CH1N. |
| 125 | PG10 | bidirectional | FT_hs I/O supplied by VDDIO2; alternates LPTIM1_IN1, OCTOSPIM_P2_IO7, SPI3_MISO(boot), USART1_RX, FMC_NE3, SAI2_FS_A, TIM15_CH1. |
| 126 | PG12 | bidirectional | FT_hs I/O supplied by VDDIO2; alternates LPTIM1_ETR, OCTOSPIM_P2_NCS, SPI3_NSS(boot), USART1_RTS_DE, FMC_NE4, SAI2_SD_A. |
| 127 | PG13 | bidirectional | FT_fhs I/O supplied by VDDIO2; alternates I2C1_SDA, SPI3_RDY, USART1_CK, FMC_A24. |
| 128 | PG14 | bidirectional | FT_fhs I/O supplied by VDDIO2; alternates LPTIM1_CH2, I2C1_SCL, FMC_A25. |
| 129 | VSS | power_in | Digital ground. |
| 130 | VDDIO2 | power_in | I/O supply for PG2-PG15 (_s I/Os); decouple with 100 nF. |
| 131 | PG15 | bidirectional | FT_hs I/O supplied by VDDIO2; alternates LPTIM1_CH1, I2C1_SMBA, OCTOSPIM_P2_DQS, DCMI_D13/PSSI_D13. |
| 132 | PB3 (JTDO/TRACESWO) | bidirectional | FT_fa I/O; JTDO/TRACESWO after reset; alternates TIM2_CH2, LPTIM1_CH1, ADF1_CCK0, I2C1_SDA, SPI1_SCK, SPI3_SCK, USART1_RTS_DE, SDMMC2_D2, SAI1_SCK_B; additional COMP2_INM2. |
| 133 | PB4 (NJTRST) | bidirectional | FT_fa I/O; NJTRST after reset with internal pull-up; alternates LPTIM1_CH2, TIM3_CH1, ADF1_SDI0, I2C3_SDA, SPI1_MISO, SPI3_MISO, USART1_CTS, UART5_RTS_DE, SDMMC2_D3; additional COMP2_INP1. |
| 134 | PB5 | bidirectional | FT_havd I/O; alternates LPTIM1_IN1, TIM3_CH2, OCTOSPIM_P1_NCLK, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI(boot), USART1_CK, UART5_CTS, COMP2_OUT; additional UCPD1_DBCC1, WKUP6. |
| 135 | PB6 | bidirectional | FT_fa I/O; alternates LPTIM1_ETR, TIM4_CH1, TIM8_BKIN2, I2C1_SCL(boot), I2C4_SCL, MDF1_SDI5, USART1_TX, TSC_G2_IO3, SAI1_FS_B; additional COMP2_INP2, WKUP3. |
| 136 | PB7 | bidirectional | FT_fhav I/O; alternates LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA(boot), I2C4_SDA, MDF1_CKI5, USART1_RX, UART4_CTS, FMC_NL; additional COMP2_INM1, PVD_IN, WKUP4. |
| 137 | PH3-BOOT0 | input | FT pin; BOOT0 boot mode selection input, EVENTOUT alternate. |
| 138 | PB8 | bidirectional | FT_f I/O; alternates TIM4_CH3, SAI1_CK1, I2C1_SCL, MDF1_CCK0, SPI3_RDY, SDMMC1_CKIN, FDCAN1_RX(boot), SAI1_MCLK_A, TIM16_CH1; additional WKUP5. |
| 139 | PB9 | bidirectional | FT_f I/O; alternates IR_OUT, TIM4_CH4, SAI1_D2, I2C1_SDA, SPI2_NSS, SDMMC1_CDIR, FDCAN1_TX(boot), SAI1_FS_A, TIM17_CH1. |
| 140 | PE0 | bidirectional | FT_h I/O; alternates TIM4_ETR, DCMI_D2/PSSI_D2, LPGPIO1_P13, FMC_NBL0, TIM16_CH1. |
| 141 | PE1 | bidirectional | FT_h I/O; alternates DCMI_D3/PSSI_D3, FMC_NBL1, TIM17_CH1. |
| 142 | VDD11 | power_in | 1.1 V core supply (SMPS output); requires 2 × 2.2 µF ±20%, ESR < 20 mΩ, rated ≥ 10 V. |
| 143 | VSS | power_in | Digital ground. |
| 144 | VDD | power_in | Digital supply, 1.71 V to 3.6 V operating. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-144(20x20) |
| Category | Embedded Processors & Controllers |
| Pins | 144 |
CAD (KiCad official)
- Symbol:
STM32U575ZIT6Q - Footprint:
Package_QFP:LQFP-144_20x20mm_P0.5mm - 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)
- 3D model files:
stm32u575zit6q-etched.step/stm32u575zit6q-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32u575zit6q.step/stm32u575zit6q.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (338 pp, sha256
6e54872aba50deff, retrieved 2026-10-06, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).