Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

ISOSD61L

STMicroelectronics · Isolated ADCs · SOIC-16-300mil

ISOSD61L from STMicroelectronics, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDISO power_in High-voltage-side supply; recommended range is 4.5 V to 5.5 V (absolute maximum -0.3 V to 6 V).
2 VIN+ power_in Positive analog input of the sigma-delta modulator; full-scale differential range is ±320 mV, recommended input voltage is -200 mV to 200 mV.
3 VIN- power_in Negative analog input of the sigma-delta modulator; forms a differential pair with VIN+ over the ±320 mV full-scale range.
4 GNDISO power_in Ground for the high-voltage (isolated) side of the device.
5 NC unconnected Test-purpose pin (Table 1 note 1); it must be connected to GND in functional mode.
6 NC unconnected Test-purpose pin (Table 1 note 1); it must be connected to GND in functional mode.
7 VDDISO power_in High-voltage-side supply; recommended range is 4.5 V to 5.5 V (absolute maximum -0.3 V to 6 V).
8 GNDISO power_in Ground for the high-voltage (isolated) side of the device.
9 GND power_in Ground for the low-voltage (digital) side of the device.
10 MDAT- output Negative LVDS serial data output of the 1-bit modulator bitstream (ISOSD61L only; NC on the single-ended ISOSD61).
11 MDAT+ output Positive LVDS serial data output of the 1-bit modulator bitstream, provided two clock cycles after the effective sampling instant with a data delay of 5 to 20 ns after the clock edge.
12 MCLKIN- input Negative LVDS modulator clock input; clock frequency 5 to 25 MHz with 48% to 52% duty cycle (ISOSD61L only; NC on the single-ended ISOSD61).
13 MCLKIN+ input Positive LVDS modulator clock input; clock frequency 5 to 25 MHz with 48% to 52% duty cycle.
14 VDD power_in Low-voltage (digital) side supply; recommended range is 3 V to 5.5 V.
15 NC unconnected Not connected; no function is stated in the datasheet.
16 GND power_in Ground for the low-voltage (digital) side of the device.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

CAD (KiCad official)

  • Symbol: ISOSD61L
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: isosd61l-etched.step / isosd61l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); isosd61l.step / isosd61l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (23 pp, sha256 e6ef0e8105c57581, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF