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AM3505AZER

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Texas Instruments Microcontrollers (MCU/MPU/SOC), BGA-484. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersam3505azerfactory-2.0.0extractor-text
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AM3505AZER

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · BGA-484

AM3505AZER from Texas Instruments, in a BGA-484. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
E3 sdrc_d0 bidirectional SDRC data bit 0 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
D3 sdrc_d1 bidirectional SDRC data bit 1 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
C3 sdrc_d2 bidirectional SDRC data bit 2 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
C2 sdrc_d3 bidirectional SDRC data bit 3 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
F3 sdrc_d4 bidirectional SDRC data bit 4 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
D2 sdrc_d5 bidirectional SDRC data bit 5 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
C1 sdrc_d6 bidirectional SDRC data bit 6 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
D1 sdrc_d7 bidirectional SDRC data bit 7 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
G2 sdrc_d8 bidirectional SDRC data bit 8 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
G3 sdrc_d9 bidirectional SDRC data bit 9 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
H3 sdrc_d10 bidirectional SDRC data bit 10 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
G4 sdrc_d11 bidirectional SDRC data bit 11 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
H4 sdrc_d12 bidirectional SDRC data bit 12 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
G1 sdrc_d13 bidirectional SDRC data bit 13 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
J3 sdrc_d14 bidirectional SDRC data bit 14 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
J1 sdrc_d15 bidirectional SDRC data bit 15 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
T3 sdrc_d16 bidirectional SDRC data bit 16 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
U3 sdrc_d17 bidirectional SDRC data bit 17 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
U4 sdrc_d18 bidirectional SDRC data bit 18 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
V4 sdrc_d19 bidirectional SDRC data bit 19 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
V1 sdrc_d20 bidirectional SDRC data bit 20 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
V2 sdrc_d21 bidirectional SDRC data bit 21 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
V5 sdrc_d22 bidirectional SDRC data bit 22 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
V3 sdrc_d23 bidirectional SDRC data bit 23 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
W3 sdrc_d24 bidirectional SDRC data bit 24 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
W4 sdrc_d25 bidirectional SDRC data bit 25 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
Y3 sdrc_d26 bidirectional SDRC data bit 26 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
Y4 sdrc_d27 bidirectional SDRC data bit 27 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
AA2 sdrc_d28 bidirectional SDRC data bit 28 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
AA3 sdrc_d29 bidirectional SDRC data bit 29 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
AA4 sdrc_d30 bidirectional SDRC data bit 30 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
AB2 sdrc_d31 bidirectional SDRC data bit 31 on VDDS (1.8 V) I/O; reset state Z, hysteresis enabled, internal PU/PD.
L4 sdrc_ba0 output SDRC bank address bit 0 output on VDDS (1.8 V), 8 pF load, reset state Z.
K5 sdrc_ba1 output SDRC bank address bit 1 output on VDDS (1.8 V), 8 pF load, reset state Z.
J5 sdrc_ba2 output SDRC bank address bit 2 output on VDDS (1.8 V), 8 pF load, reset state Z.
M3 sdrc_a0 output SDRC address bit 0 output on VDDS (1.8 V), 8 pF load, reset state Z.
M4 sdrc_a1 output SDRC address bit 1 output on VDDS (1.8 V), 8 pF load, reset state Z.
M5 sdrc_a2 output SDRC address bit 2 output on VDDS (1.8 V), 8 pF load, reset state Z.
N3 sdrc_a3 output SDRC address bit 3 output on VDDS (1.8 V), 8 pF load, reset state Z.
N2 sdrc_a4 output SDRC address bit 4 output on VDDS (1.8 V), 8 pF load, reset state Z.
N4 sdrc_a5 output SDRC address bit 5 output on VDDS (1.8 V), 8 pF load, reset state Z.
P3 sdrc_a6 output SDRC address bit 6 output on VDDS (1.8 V), 8 pF load, reset state Z.
P2 sdrc_a7 output SDRC address bit 7 output on VDDS (1.8 V), 8 pF load, reset state Z.
P1 sdrc_a8 output SDRC address bit 8 output on VDDS (1.8 V), 8 pF load, reset state Z.
P4 sdrc_a9 output SDRC address bit 9 output on VDDS (1.8 V), 8 pF load, reset state Z.
R1 sdrc_a10 output SDRC address bit 10 output on VDDS (1.8 V), 8 pF load, reset state Z.
R2 sdrc_a11 output SDRC address bit 11 output on VDDS (1.8 V), 8 pF load, reset state Z.
R3 sdrc_a12 output SDRC address bit 12 output on VDDS (1.8 V), 8 pF load, reset state Z.
R4 sdrc_a13 output SDRC address bit 13 output on VDDS (1.8 V), 8 pF load, reset state Z.
T2 sdrc_a14 output SDRC address bit 14 output on VDDS (1.8 V), 8 pF load, reset state Z.
J4 sdrc_ncs0 output SDRC chip select 0 (active low) output on VDDS (1.8 V), 8 pF load, reset state Z.
K4 sdrc_ncs1 output SDRC chip select 1 (active low) output on VDDS (1.8 V), 8 pF load, reset state Z.
L1 sdrc_clk output SDRC differential clock output (true) on VDDS (1.8 V), 8 pF load, reset state Z.
L2 sdrc_nclk output SDRC differential clock output (complement) on VDDS (1.8 V), 8 pF load, reset state Z.
K3 sdrc_cke0 output SDRC clock enable 0 on VDDS (1.8 V), 8 pF load, reset state 0 with pulldown; mode 7 provides sdrc_cke0_safe.
K1 sdrc_nras output SDRC row address strobe output on VDDS (1.8 V), 8 pF load, reset state Z.
L3 sdrc_ncas output SDRC column address strobe output on VDDS (1.8 V), 8 pF load, reset state Z.
K2 sdrc_nwe output SDRC write enable output on VDDS (1.8 V), 8 pF load, reset state Z.
F4 sdrc_dm0 output SDRC data mask 0 output on VDDS (1.8 V), 8 pF load, reset state Z.
J2 sdrc_dm1 output SDRC data mask 1 output on VDDS (1.8 V), 8 pF load, reset state Z.
T4 sdrc_dm2 output SDRC data mask 2 output on VDDS (1.8 V), 8 pF load, reset state Z.
AB3 sdrc_dm3 output SDRC data mask 3 output on VDDS (1.8 V), 8 pF load, reset state Z.
E2 sdrc_dqs0p bidirectional SDRC data strobe 0 true on VDDS (1.8 V), reset state Z, hysteresis enabled.
H2 sdrc_dqs1p bidirectional SDRC data strobe 1 true on VDDS (1.8 V), reset state Z, hysteresis enabled.
U1 sdrc_dqs2p bidirectional SDRC data strobe 2 true on VDDS (1.8 V), reset state Z, hysteresis enabled.
Y1 sdrc_dqs3p bidirectional SDRC data strobe 3 true on VDDS (1.8 V), reset state Z, hysteresis enabled.
E1 sdrc_dqs0n bidirectional SDRC data strobe 0 complement on VDDS (1.8 V), reset state Z.
H1 sdrc_dqs1n bidirectional SDRC data strobe 1 complement on VDDS (1.8 V), reset state Z.
U2 sdrc_dqs2n bidirectional SDRC data strobe 2 complement on VDDS (1.8 V), reset state Z.
Y2 sdrc_dqs3n bidirectional SDRC data strobe 3 complement on VDDS (1.8 V), reset state Z.
T1 sdrc_odt output SDRC on-die termination control on VDDS (1.8 V), 8 pF load, reset state Z.
F2 sdrc_strben0 output SDRC read strobe enable 0 on VDDS (1.8 V), 8 pF load, reset state Z.
F1 sdrc_strben_dly0 output SDRC read strobe enable delayed 0 on VDDS (1.8 V), 8 pF load, reset state Z.
W1 sdrc_strben1 output SDRC read strobe enable 1 on VDDS (1.8 V), 8 pF load, reset state Z.
W2 sdrc_strben_dly1 output SDRC read strobe enable delayed 1 on VDDS (1.8 V), 8 pF load, reset state Z.
W5 gpmc_a1 output GPMC address bit 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
Y5 gpmc_a2 output GPMC address bit 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
AB4 gpmc_a3 output GPMC address bit 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
AA5 gpmc_a4 output GPMC address bit 4 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
AB5 gpmc_a5 output GPMC address bit 5 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
AB6 gpmc_a6 output GPMC address bit 6 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
AA6 gpmc_a7 output GPMC address bit 7 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
W6 gpmc_a8 output GPMC address bit 8 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
AB7 gpmc_a9 output GPMC address bit 9 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq2 in mode 1.
Y6 gpmc_a10 output GPMC address bit 10 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq3 in mode 1.
AA7 gpmc_d0 bidirectional GPMC data bit 0 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, internal PU/PD.
Y7 gpmc_d1 bidirectional GPMC data bit 1 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled.
W7 gpmc_d2 bidirectional GPMC data bit 2 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled.
AA9 gpmc_d3 bidirectional GPMC data bit 3 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled.
Y8 gpmc_d4 bidirectional GPMC data bit 4 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled.
AA8 gpmc_d5 bidirectional GPMC data bit 5 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled.
AB8 gpmc_d6 bidirectional GPMC data bit 6 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled.
W8 gpmc_d7 bidirectional GPMC data bit 7 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled.
W10 gpmc_d8 bidirectional GPMC data bit 8 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_44 in mode 4.
AB9 gpmc_d9 bidirectional GPMC data bit 9 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_45 in mode 4.
AB10 gpmc_d10 bidirectional GPMC data bit 10 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_46 in mode 4.
W9 gpmc_d11 bidirectional GPMC data bit 11 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_47 in mode 4.
AA10 gpmc_d12 bidirectional GPMC data bit 12 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_48 in mode 4.
Y9 gpmc_d13 bidirectional GPMC data bit 13 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_49 in mode 4.
V10 gpmc_d14 bidirectional GPMC data bit 14 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_50 in mode 4.
V9 gpmc_d15 bidirectional GPMC data bit 15 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also gpio_51 in mode 4.
Y10 gpmc_ncs0 output GPMC chip select 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance, no pull.
Y11 gpmc_ncs1 output GPMC chip select 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance; also gpio_52 in mode 4.
Y12 gpmc_ncs2 output GPMC chip select 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpt9_pwm_evt and gpio_53.
V12 gpmc_ncs3 output GPMC chip select 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq0, gpt10_pwm_evt, gpio_54.
AA11 gpmc_ncs4 output GPMC chip select 4 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq1, gpt9_pwm_evt, gpio_55.
W12 gpmc_ncs5 output GPMC chip select 5 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq2, gpt10_pwm_evt, gpio_56.
AA12 gpmc_ncs6 output GPMC chip select 6 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also sys_ndmareq3, gpt11_pwm_evt, gpio_57.
V11 gpmc_ncs7 output GPMC chip select 7 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpmc_io_dir, gpt8_pwm_evt, gpio_58.
AB13 gpmc_clk output GPMC clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_59.
AA14 gpmc_nadv_ale output GPMC address valid / address latch enable on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance.
AB14 gpmc_noe output GPMC output enable (active low) on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance.
AA15 gpmc_nwe output GPMC write enable (active low) on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 high-impedance.
W11 gpmc_nbe0_cle output GPMC byte enable 0 / command latch enable on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_60.
Y15 gpmc_nbe1 output GPMC byte enable 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpio_61.
W14 gpmc_nwp output GPMC write protect on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_62.
V13 gpmc_wait0 input GPMC wait input 0 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup, hysteresis enabled.
AA16 gpmc_wait1 input GPMC wait input 1 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also uart4_tx and gpio_63.
Y14 gpmc_wait2 input GPMC wait input 2 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also uart4_rx and gpio_64.
V14 gpmc_wait3 input GPMC wait input 3 on VDDSHV (1.8 V/3.3 V), reset state 1 with pullup; also sys_ndmareq1, uart3_ctsn and gpio_65.
B22 dss_pclk output Display subsystem pixel clock on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup.
B21 dss_hsync output Display subsystem horizontal sync on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup.
B20 dss_vsync output Display subsystem vertical sync on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup.
B19 dss_acbias output Display subsystem AC bias output on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
A20 dss_data0 output Display subsystem data bit 0 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_cts.
A19 dss_data1 output Display subsystem data bit 1 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_rts.
A18 dss_data2 output Display subsystem data bit 2 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
B18 dss_data3 output Display subsystem data bit 3 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
A17 dss_data4 output Display subsystem data bit 4 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart3_rx_irrx.
C18 dss_data5 output Display subsystem data bit 5 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart3_tx_irtx.
D17 dss_data6 output Display subsystem data bit 6 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_tx.
B16 dss_data7 output Display subsystem data bit 7 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also uart1_rx.
B17 dss_data8 output Display subsystem data bit 8 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
C17 dss_data9 output Display subsystem data bit 9 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
C16 dss_data10 output Display subsystem data bit 10 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
D16 dss_data11 output Display subsystem data bit 11 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
D14 dss_data12 output Display subsystem data bit 12 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
A16 dss_data13 output Display subsystem data bit 13 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
D15 dss_data14 output Display subsystem data bit 14 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
B15 dss_data15 output Display subsystem data bit 15 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
A15 dss_data16 output Display subsystem data bit 16 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
A14 dss_data17 output Display subsystem data bit 17 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
C13 dss_data18 output Display subsystem data bit 18 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_clk.
C15 dss_data19 output Display subsystem data bit 19 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_simo.
A13 dss_data20 output Display subsystem data bit 20 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_somi.
B13 dss_data21 output Display subsystem data bit 21 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_cs0.
C14 dss_data22 output Display subsystem data bit 22 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown; also mcspi3_cs1.
B14 dss_data23 output Display subsystem data bit 23 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
AB21 ccdc_pclk bidirectional CCDC pixel clock on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg0 and gpio_94.
AA21 ccdc_field bidirectional CCDC field signal on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also ccdc_data8, uart4_tx and i2c3_scl.
Y21 ccdc_hd bidirectional CCDC horizontal sync on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also uart4_rts.
Y22 ccdc_vd bidirectional CCDC vertical sync on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also uart4_cts.
W21 ccdc_wen bidirectional CCDC write enable on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also ccdc_data9 and uart4_rx.
W22 ccdc_data0 input CCDC data bit 0 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also i2c3_sda.
W20 ccdc_data1 input CCDC data bit 1 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown.
V21 ccdc_data2 input CCDC data bit 2 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg4.
V19 ccdc_data3 input CCDC data bit 3 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg5.
V22 ccdc_data4 input CCDC data bit 4 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg6.
U20 ccdc_data5 input CCDC data bit 5 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown; also hw_dbg7.
V20 ccdc_data6 input CCDC data bit 6 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown.
U19 ccdc_data7 input CCDC data bit 7 input on VDDSHV (1.8 V/3.3 V), 15 pF load, reset state 0 with pulldown.
U21 rmii_mdio_data bidirectional EMAC RMII management data on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data8 and gpio_107.
U22 rmii_mdio_clk output EMAC RMII management clock on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data9 and gpio_108.
T19 rmii_rxd0 input EMAC RMII receive data bit 0 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data10.
T20 rmii_rxd1 input EMAC RMII receive data bit 1 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data11.
T21 rmii_crs_dv input EMAC RMII carrier sense / receive data valid on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup.
R22 rmii_rxer input EMAC RMII receive error on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup; also ccdc_data13.
T22 rmii_txd0 output EMAC RMII transmit data bit 0 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup.
R20 rmii_txd1 output EMAC RMII transmit data bit 1 on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup.
R19 rmii_txen output EMAC RMII transmit enable on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup.
R21 rmii_50mhz_clk input EMAC RMII 50 MHz reference clock input on VDDSHV (1.8 V/3.3 V), 25 pF load, reset state 1 with pullup.
E5 mcbsp2_fsx bidirectional McBSP2 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
D5 mcbsp2_clkx bidirectional McBSP2 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
C5 mcbsp2_dr input McBSP2 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
E4 mcbsp2_dx bidirectional McBSP2 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
P22 mmc1_clk output MMC1 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
N21 mmc1_cmd bidirectional MMC1 command on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
P21 mmc1_dat0 bidirectional MMC1 data bit 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_clk.
N20 mmc1_dat1 bidirectional MMC1 data bit 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_simo.
P19 mmc1_dat2 bidirectional MMC1 data bit 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_somi.
P20 mmc1_dat3 bidirectional MMC1 data bit 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi2_cs0.
N22 mmc1_dat4 bidirectional MMC1 data bit 4 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_126.
N19 mmc1_dat5 bidirectional MMC1 data bit 5 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_127.
N18 mmc1_dat6 bidirectional MMC1 data bit 6 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_128.
P18 mmc1_dat7 bidirectional MMC1 data bit 7 on VDDSHV (1.8 V/3.3 V), reset state 0 with pulldown; no hysteresis; also gpio_129.
M21 mmc2_clk output MMC2 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi3_clk, uart4_cts.
M20 mmc2_cmd bidirectional MMC2 command on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_simo and uart4_rts.
K20 mmc2_dat0 bidirectional MMC2 data bit 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_somi and uart4_tx.
L19 mmc2_dat1 bidirectional MMC2 data bit 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also uart4_rx.
M18 mmc2_dat2 bidirectional MMC2 data bit 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_cs1.
K21 mmc2_dat3 bidirectional MMC2 data bit 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mcspi3_cs0.
L18 mmc2_dat4 bidirectional MMC2 data bit 4 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dir_data0 and mmc3_dat0.
L20 mmc2_dat5 bidirectional MMC2 data bit 5 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dir_data1 and mmc3_dat1.
L21 mmc2_dat6 bidirectional MMC2 data bit 6 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dir_cmd and mmc3_dat2.
M19 mmc2_dat7 bidirectional MMC2 data bit 7 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_clkin and mmc3_dat3.
C4 mcbsp3_dx bidirectional McBSP3 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_cts.
B4 mcbsp3_dr input McBSP3 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_rts.
D4 mcbsp3_clkx bidirectional McBSP3 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_tx.
A4 mcbsp3_fsx bidirectional McBSP3 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart2_rx.
A5 uart2_cts input UART2 clear to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
B5 uart2_rts output UART2 request to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
D6 uart2_tx output UART2 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
C6 uart2_rx input UART2 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
C22 uart1_tx output UART1 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
C21 uart1_rts output UART1 request to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
C19 uart1_cts input UART1 clear to send on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
C20 uart1_rx input UART1 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcbsp1_clkr and mcspi4_clk.
A3 mcbsp4_clkx bidirectional McBSP4 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_txse0.
B3 mcbsp4_dr input McBSP4 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_rxrcv.
A2 mcbsp4_dx bidirectional McBSP4 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_txdat.
B2 mcbsp4_fsx bidirectional McBSP4 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mm_fsusb3_txen_n.
B11 mcbsp1_clkr bidirectional McBSP1 receive clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_clk.
D11 mcbsp1_fsr bidirectional McBSP1 frame sync receive on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown.
C10 mcbsp1_dx bidirectional McBSP1 transmit data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_simo and mcbsp3_dx.
C9 mcbsp1_dr input McBSP1 receive data on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_somi and mcbsp3_dr.
E11 mcbsp_clks input McBSP sample rate clock input on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart1_cts.
C11 mcbsp1_fsx bidirectional McBSP1 frame sync transmit on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcspi4_cs0 and mcbsp3_fsx.
C8 mcbsp1_clkx bidirectional McBSP1 transmit clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mcbsp3_clkx.
W15 uart3_cts_rctx bidirectional UART3 clear to send (input) / remote TX (output) on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
W13 uart3_rts_sd output UART3 request to send / IR enable output on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
AA13 uart3_rx_irrx input UART3 receive data / IR and remote RX input on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
Y13 uart3_tx_irtx output UART3 transmit data / IR TX output on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup.
A6 usb0_dp bidirectional USB0 D+ differential signal pair, 5.0 V tolerant, with internal PU/PD.
B6 usb0_dm bidirectional USB0 D- differential signal pair, 5.0 V tolerant, with internal PU/PD.
C7 usb0_vbus passive USB0 VBUS analog input; tie to USB connector (host/device) or external charge pump and VBUS (OTG), VDDA3P3V_USBPHY 3.3 V.
B7 usb0_id passive USB0 operating mode identification (analog) pin on VDDA3P3V_USBPHY (3.3 V).
A7 usb0_drvvbus output Digital output controlling external VBUS supply on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also uart3_tx_irtx and gpio_125.
AB15 hecc1_txd output HECC1 CAN transmit on VDDSHV (1.8 V/3.3 V), 24 pF load, reset state 1 with pullup; also uart3_rx_irrx and gpio_130.
AB16 hecc1_rxd input HECC1 CAN receive on VDDSHV (1.8 V/3.3 V), 24 pF load, reset state 1 with pullup; also uart3_rts_sd and gpio_131.
AA17 i2c1_scl bidirectional I2C1 clock, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup.
AB17 i2c1_sda bidirectional I2C1 data, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup.
Y17 i2c2_scl bidirectional I2C2 clock, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_168.
Y16 i2c2_sda bidirectional I2C2 data, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_183.
W16 i2c3_scl bidirectional I2C3 clock, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_184.
W17 i2c3_sda bidirectional I2C3 data, open-drain, on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup; also gpio_185.
B9 hdq_sio bidirectional HDQ/1-Wire single-wire data on VDDSHV (1.8 V/3.3 V), 40 pF load, reset state 1 with pullup.
K22 mcspi1_clk bidirectional McSPI1 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dat4.
K19 mcspi1_simo bidirectional McSPI1 SIMO on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dat5.
J18 mcspi1_somi bidirectional McSPI1 SOMI on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also mmc2_dat6.
K18 mcspi1_cs0 bidirectional McSPI1 chip select 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mmc2_dat7.
J20 mcspi1_cs1 output McSPI1 chip select 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mmc3_cmd.
J19 mcspi1_cs2 output McSPI1 chip select 2 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also mmc3_clk.
J21 mcspi1_cs3 output McSPI1 chip select 3 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also hsusb2_data2 and mm_fsusb2_txdat.
J22 mcspi2_clk bidirectional McSPI2 clock on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also hsusb2_data7.
H20 mcspi2_simo bidirectional McSPI2 SIMO on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpt9_pwm_evt and hsusb2_data4.
H22 mcspi2_somi bidirectional McSPI2 SOMI on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpt10_pwm_evt and hsusb2_data5.
H21 mcspi2_cs0 bidirectional McSPI2 chip select 0 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpt11_pwm_evt and hsusb2_data6.
H19 mcspi2_cs1 output McSPI2 chip select 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; also gpt8_pwm_evt and hsusb2_data3.
A8 sys_32k input 32 kHz clock input on VDDSHV (1.8 V/3.3 V), 30 pF load, high-impedance at reset.
A10 sys_xtalin input Oscillator crystal input on VDDSOSC (1.8 V), high-impedance at reset.
A9 sys_xtalout output Oscillator crystal output on VDDSOSC (1.8 V), high-impedance at reset.
B8 sys_clkreq bidirectional System clock request on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 high-impedance; also gpio_1.
AB18 sys_nirq input System interrupt input on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pullup; also gpio_0.
AA18 sys_nrespwron input Power-on reset input on VDDSHV (1.8 V/3.3 V), high-impedance at reset.
Y18 sys_nreswarm bidirectional Warm reset bidirectional on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 0 with pulldown; open-drain function on gpio_30.
AB19 sys_boot0 input Boot configuration input 0 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_2.
AB20 sys_boot1 input Boot configuration input 1 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_3.
W18 sys_boot2 input Boot configuration input 2 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_4.
AA19 sys_boot3 input Boot configuration input 3 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_5.
V18 sys_boot4 input Boot configuration input 4 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also mmc2_dir_data2 and gpio_6.
Y19 sys_boot5 input Boot configuration input 5 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also mmc2_dir_data3 and gpio_7.
W19 sys_boot6 input Boot configuration input 6 on VDDSHV (1.8 V/3.3 V), high-impedance at reset; also gpio_8.
AA20 sys_boot7 input Boot configuration input 7 on VDDSHV (1.8 V/3.3 V), high-impedance at reset with pullup.
Y20 sys_boot8 input Boot configuration input 8 on VDDSHV (1.8 V/3.3 V), high-impedance at reset with pullup.
E9 sys_clkout1 output System clock output 1 on VDDSHV (1.8 V/3.3 V), 30 pF load, reset state 1 with pulldown; mux 0 if sys_boot6 is pulled down (clock master); also gpio_10.
E10 sys_clkout2 output System clock output 2 on VDDSHV (1.8 V/3.3 V), 10 pF load, reset state 0 with pulldown; also gpio_186.
D13 jtag_ntrst input JTAG test reset input on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
E14 jtag_tck input JTAG test clock input on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 with pulldown.
C12 jtag_rtck output JTAG return test clock output on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 high-impedance.
A12 jtag_tms_tmsc bidirectional JTAG test mode select / TMSC on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup.
B12 jtag_tdi input JTAG test data input on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup.
D12 jtag_tdo output JTAG test data output on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 0 high-impedance.
E13 jtag_emu0 bidirectional JTAG emulation pin 0 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup; also gpio_11.
E12 jtag_emu1 bidirectional JTAG emulation pin 1 on VDDSHV (1.8 V/3.3 V), 20 pF load, reset state 1 with pullup; also gpio_31.
G22 etk_clk output ETK trace clock on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcbsp5_clkx, mmc3_clk, hsusb1_stp and gpio_12.
G21 etk_ctl output ETK trace control on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mmc3_cmd, hsusb1_clk and gpio_13.
G20 etk_d0 output ETK trace data bit 0 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcspi3_simo and hsusb1_data0.
F22 etk_d1 output ETK trace data bit 1 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcspi3_somi and hsusb1_data1.
F20 etk_d2 output ETK trace data bit 2 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 1 with pullup; also mcspi3_cs0 and hsusb1_data2.
G19 etk_d3 output ETK trace data bit 3 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pullup; also mcspi3_clk and hsusb1_data7.
E19 etk_d4 output ETK trace data bit 4 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcbsp5_dr and hsusb1_data4.
F21 etk_d5 output ETK trace data bit 5 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcbsp5_fsx and hsusb1_data5.
F19 etk_d6 output ETK trace data bit 6 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcbsp5_dx and hsusb1_data6.
E21 etk_d7 output ETK trace data bit 7 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcspi3_cs1 and hsusb1_data3.
D22 etk_d8 output ETK trace data bit 8 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mmc3_dat6 and hsusb1_dir.
D21 etk_d9 output ETK trace data bit 9 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mmc3_dat5 and hsusb1_nxt.
E22 etk_d10 output ETK trace data bit 10 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also uart1_rx and hsusb2_clk.
E20 etk_d11 output ETK trace data bit 11 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also mcspi3_clk and hsusb2_stp.
E18 etk_d12 output ETK trace data bit 12 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_dir.
D20 etk_d13 output ETK trace data bit 13 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_nxt.
D19 etk_d14 output ETK trace data bit 14 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_data0.
D18 etk_d15 output ETK trace data bit 15 on VDDSHV (1.8 V/3.3 V), 9/25 pF load, reset state 0 with pulldown; also hsusb2_data1.
M2 ddr_padref passive DDR pad reference voltage on VDDS (1.8 V).
J8 VDD_CORE power_in Core logic supply, 1.2 V nominal.
J10 VDD_CORE power_in Core logic supply, 1.2 V nominal.
J12 VDD_CORE power_in Core logic supply, 1.2 V nominal.
J14 VDD_CORE power_in Core logic supply, 1.2 V nominal.
J16 VDD_CORE power_in Core logic supply, 1.2 V nominal.
K9 VDD_CORE power_in Core logic supply, 1.2 V nominal.
K11 VDD_CORE power_in Core logic supply, 1.2 V nominal.
K13 VDD_CORE power_in Core logic supply, 1.2 V nominal.
K15 VDD_CORE power_in Core logic supply, 1.2 V nominal.
L8 VDD_CORE power_in Core logic supply, 1.2 V nominal.
L10 VDD_CORE power_in Core logic supply, 1.2 V nominal.
L12 VDD_CORE power_in Core logic supply, 1.2 V nominal.
L14 VDD_CORE power_in Core logic supply, 1.2 V nominal.
M7 VDD_CORE power_in Core logic supply, 1.2 V nominal.
M9 VDD_CORE power_in Core logic supply, 1.2 V nominal.
M11 VDD_CORE power_in Core logic supply, 1.2 V nominal.
M13 VDD_CORE power_in Core logic supply, 1.2 V nominal.
M15 VDD_CORE power_in Core logic supply, 1.2 V nominal.
N8 VDD_CORE power_in Core logic supply, 1.2 V nominal.
N10 VDD_CORE power_in Core logic supply, 1.2 V nominal.
N12 VDD_CORE power_in Core logic supply, 1.2 V nominal.
N14 VDD_CORE power_in Core logic supply, 1.2 V nominal.
P7 VDD_CORE power_in Core logic supply, 1.2 V nominal.
P9 VDD_CORE power_in Core logic supply, 1.2 V nominal.
P11 VDD_CORE power_in Core logic supply, 1.2 V nominal.
P13 VDD_CORE power_in Core logic supply, 1.2 V nominal.
P15 VDD_CORE power_in Core logic supply, 1.2 V nominal.
R8 VDD_CORE power_in Core logic supply, 1.2 V nominal.
R10 VDD_CORE power_in Core logic supply, 1.2 V nominal.
R12 VDD_CORE power_in Core logic supply, 1.2 V nominal.
R14 VDD_CORE power_in Core logic supply, 1.2 V nominal.
L17 VDDS_SRAM_MPU power_in SRAM supply for the MPU domain, 1.8 V.
J6 VDDS_SRAM_CORE_BG power_in SRAM supply for the core domain (bandgap), 1.8 V.
M17 CAP_VDD_SRAM_MPU power_in SRAM core voltage capacitor node for the MPU domain, 1.2 V.
K6 CAP_VDD_SRAM_CORE power_in SRAM core voltage capacitor node for the core domain, 1.2 V.
K17 VDDS_DPLL_MPU_USBHOST power_in DPLL supply for MPU and USB host clocks, 1.8 V; requires the noise filter in Table 5-19.
F11 VDDS_DPLL_PER_CORE power_in DPLL supply for peripheral and core clocks, 1.8 V; requires the noise filter in Table 5-19.
F7 VDDA3P3V_USBPHY power_in USB PHY analog supply, 3.3 V.
D7 VDDA1P8V_USBPHY power_in USB PHY analog supply, 1.8 V.
E7 CAP_VDDA1_P2LDO_USBPHY passive USB PHY internal LDO capacitor node, 1.2 V (printed name wraps across lines).
A21 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
B1 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
E15 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
E17 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
F12 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
F14 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
F18 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
G10 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
G12 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
G13 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
G8 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
G17 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
H18 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
J17 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
L22 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
N16 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
P17 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
R16 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
R18 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
T9 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
T11 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
T13 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
T17 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
U8 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
U10 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
U12 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
U14 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
U16 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
U18 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
V7 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
V8 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
V17 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
AA22 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
AB11 VDDSHV power_in I/O supply for 1.8 V/3.3 V peripheral buffers.
F5 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
F16 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
G15 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
H5 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
K7 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
L6 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
L16 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
N1 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
N5 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
N6 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
P5 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
R6 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
T5 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
T7 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
T15 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
U6 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
AA1 VDDS power_in I/O supply for DDR2/mDDR interface buffers, 1.8 V.
L5 VREFSSTL input DDR SSTL reference voltage input, 0.5 × VDDS.
G9 VDDSOSC power_in Oscillator supply, 1.8 V.
B10 VSSOSC power_in Oscillator ground.
A1 VSS power_in Ground.
A11 VSS power_in Ground.
A22 VSS power_in Ground.
E6 VSS power_in Ground.
E16 VSS power_in Ground.
F6 VSS power_in Ground.
F13 VSS power_in Ground.
F15 VSS power_in Ground.
F17 VSS power_in Ground.
G5 VSS power_in Ground.
G7 VSS power_in Ground.
G11 VSS power_in Ground.
G14 VSS power_in Ground.
G16 VSS power_in Ground.
G18 VSS power_in Ground.
H6 VSS power_in Ground.
H7 VSS power_in Ground.
H8 VSS power_in Ground.
H9 VSS power_in Ground.
H10 VSS power_in Ground.
H11 VSS power_in Ground.
H12 VSS power_in Ground.
H13 VSS power_in Ground.
H14 VSS power_in Ground.
H15 VSS power_in Ground.
H16 VSS power_in Ground.
H17 VSS power_in Ground.
J9 VSS power_in Ground.
J11 VSS power_in Ground.
J13 VSS power_in Ground.
J15 VSS power_in Ground.
K8 VSS power_in Ground.
K10 VSS power_in Ground.
K12 VSS power_in Ground.
K14 VSS power_in Ground.
K16 VSS power_in Ground.
L7 VSS power_in Ground.
L9 VSS power_in Ground.
L11 VSS power_in Ground.
L13 VSS power_in Ground.
L15 VSS power_in Ground.
M1 VSS power_in Ground.
M6 VSS power_in Ground.
M8 VSS power_in Ground.
M10 VSS power_in Ground.
M12 VSS power_in Ground.
M14 VSS power_in Ground.
M16 VSS power_in Ground.
M22 VSS power_in Ground.
N7 VSS power_in Ground.
N9 VSS power_in Ground.
N11 VSS power_in Ground.
N13 VSS power_in Ground.
N15 VSS power_in Ground.
N17 VSS power_in Ground.
P6 VSS power_in Ground.
P8 VSS power_in Ground.
P10 VSS power_in Ground.
P12 VSS power_in Ground.
P14 VSS power_in Ground.
P16 VSS power_in Ground.
R5 VSS power_in Ground.
R7 VSS power_in Ground.
R9 VSS power_in Ground.
R11 VSS power_in Ground.
R13 VSS power_in Ground.
R15 VSS power_in Ground.
R17 VSS power_in Ground.
T6 VSS power_in Ground.
T8 VSS power_in Ground.
T10 VSS power_in Ground.
T12 VSS power_in Ground.
T14 VSS power_in Ground.
T16 VSS power_in Ground.
T18 VSS power_in Ground.
U5 VSS power_in Ground.
U7 VSS power_in Ground.
U9 VSS power_in Ground.
U11 VSS power_in Ground.
U13 VSS power_in Ground.
U15 VSS power_in Ground.
U17 VSS power_in Ground.
V6 VSS power_in Ground.
AB1 VSS power_in Ground.
AB12 VSS power_in Ground.
AB22 VSS power_in Ground.
D8 NC unconnected No connect; must be left unconnected for proper operation.
D9 NC unconnected No connect; must be left unconnected for proper operation.
D10 NC unconnected No connect; must be left unconnected for proper operation.
E8 NC unconnected No connect; must be left unconnected for proper operation.
F8 NC unconnected No connect; must be left unconnected for proper operation.
F9 NC unconnected No connect; must be left unconnected for proper operation.
F10 NC unconnected No connect; must be left unconnected for proper operation.
J7 NC unconnected No connect; must be left unconnected for proper operation.
G6 NC unconnected No connect; must be left unconnected for proper operation.
V15 Reserved passive Reserved ball; must be pulled up via a 10 kΩ resistor for proper operation.
V16 Reserved passive Reserved ball; must be pulled up via a 10 kΩ resistor for proper operation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package BGA-484
Category Embedded Processors & Controllers
Pins 484

CAD (KiCad official)

  • Symbol: AM3505AZER
  • Footprint: Package_BGA:BGA-484_23.0x23.0mm_Layout22x22_P1.0mm
  • 3D model: BGA-484 (KiCad packages3D, STEP)
  • 3D model files: am3505azer-etched.step / am3505azer-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); am3505azer.step / am3505azer.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (226 pp, sha256 82e95be0c6355b7d, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF