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ADUM1100ARZ-RL7

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Analog Devices Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADUM1100ARZ-RL7

Analog Devices · Digital Isolators · SOIC-8

ADUM1100ARZ-RL7 from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Input supply voltage, 3.0 V to 5.5 V; pin 1 and pin 3 are internally connected, and either or both may be used for VDD1.
2 VI input Logic input; for 5 V operation VIH is 2.0 V minimum and VIL is 0.8 V maximum, and for 3.3 V operation VIH is 1.5 V minimum and VIL is 0.5 V maximum, with 300 mV of input hysteresis.
3 VDD1 power_in Input supply voltage, 3.0 V to 5.5 V; pin 3 is internally connected to pin 1, and either or both may be used for VDD1.
4 GND1 power_in Input ground reference for the side 1 circuitry; all voltages are relative to this ground.
5 GND2 power_in Output ground reference; pin 5 is internally connected to pin 7, and either or both may be used for GND2.
6 VO output Logic output; VO returns to the VI state within 1 µs of power restoration, and the output is referenced to VDD2 and GND2.
7 GND2 power_in Output ground reference; pin 7 is internally connected to pin 5, and either or both may be used for GND2.
8 VDD2 power_in Output supply voltage, 3.0 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Supply Current, Quiescent IDD1 (Q) 0.3 0.8 mA VI = 0 V or VDD1 4
Output Supply Current, Quiescent IDD2 (Q) 0.01 0.06 mA VI = 0 V or VDD1 4
Input Supply Current (25 Mbps) IDD1 (25) 2.2 3.5 mA 12.5 MHz logic signal frequency 4
Output Supply Current (25 Mbps) IDD2 (25) 0.5 1 mA 12.5 MHz logic signal frequency 4
Input Current II -10 0.01 10 µA 0 V ≤ VIN ≤ VDD1 4
Logic High Output Voltage (min printed as VDD2 − 0.1) VOH 5 V IO = −20 μA, VI = VIH 4
Logic High Output Voltage (min printed as VDD2 − 0.8) VOH 4.6 V IO = −4 mA, VI = VIH 4
Logic Low Output Voltage VOL 0 0.1 V IO = 20 μA, VI = VIL 4
Logic Low Output Voltage VOL 0.03 0.1 V IO = 400 μA, VI = VIL 4
Logic Low Output Voltage VOL 0.3 0.8 V IO = 4 mA, VI = VIL 4
Minimum Pulse Width (ADuM1100AR) PW 40 ns CL = 15 pF, CMOS signal levels 4
Maximum Data Rate (ADuM1100AR) 25 Mbps CL = 15 pF, CMOS signal levels 4
Propagation Delay Time to Logic Low Output (5 V operation) tPHL 10.5 18 ns CL = 15 pF, CMOS signal levels 4
Propagation Delay Time to Logic High Output (5 V operation) tPLH 10.5 18 ns CL = 15 pF, CMOS signal levels 4
Pulse Width Distortion /tPLH − tPHL/ (5 V operation) PWD 0.5 2 ns CL = 15 pF, CMOS signal levels 4
Propagation Delay Skew (Equal Temperature) (5 V operation) tPSK1 8 ns CL = 15 pF, CMOS signal levels 4
Propagation Delay Skew (Equal Temperature, Supplies) (5 V operation) tPSK2 6 ns CL = 15 pF, CMOS signal levels 4
Output Rise/Fall Time (5 V operation) tR, tF 3 ns CL = 15 pF, CMOS signal levels 4
Common-Mode Transient Immunity at Logic Low/High Output (5 V operation) /CML/, /CMH/ 25 35 kV/µs VI = 0 V or VDD1, VCM = 1000 V, transient magnitude = 800 V 4
Input Supply Current, Quiescent (3.3 V operation) IDD1 (Q) 0.1 0.3 mA VI = 0 V or VDD1 6
Output Supply Current, Quiescent (3.3 V operation) IDD2 (Q) 0.005 0.04 mA VI = 0 V or VDD1 6
Input Supply Current (25 Mbps) (3.3 V operation) IDD1 (25) 2 2.8 mA 12.5 MHz logic signal frequency 6
Output Supply Current (25 Mbps) (3.3 V operation) IDD2 (25) 0.3 0.7 mA 12.5 MHz logic signal frequency 6
Input Current II -10 0.01 10 µA 0 V ≤ VIN ≤ VDD1 6
Logic High Output Voltage (min printed as VDD2 − 0.1) (3.3 V operation) VOH 3.3 V IO = −20 μA, VI = VIH 6
Logic High Output Voltage (min printed as VDD2 − 0.5) (3.3 V operation) VOH 3 V IO = −2.5 mA, VI = VIH 6
Logic Low Output Voltage (3.3 V operation) VOL 0 0.1 V IO = 20 μA, VI = VIL 6
Logic Low Output Voltage (3.3 V operation) VOL 0.04 0.1 V IO = 400 μA, VI = VIL 6
Logic Low Output Voltage (3.3 V operation) VOL 0.3 0.4 V IO = 2.5 mA, VI = VIL 6
Minimum Pulse Width (ADuM1100AR) PW 40 ns CL = 15 pF, CMOS signal levels 6
Maximum Data Rate (ADuM1100AR) 25 Mbps CL = 15 pF, CMOS signal levels 6
Propagation Delay Time to Logic Low Output (3.3 V operation) tPHL 14.5 28 ns CL = 15 pF, CMOS signal levels 6
Propagation Delay Time to Logic High Output (3.3 V operation) tPLH 15 28 ns CL = 15 pF, CMOS signal levels 6
Pulse Width Distortion /tPLH − tPHL/ (3.3 V operation) PWD 0.5 3 ns CL = 15 pF, CMOS signal levels 6
Propagation Delay Skew (Equal Temperature) (3.3 V operation) tPSK1 15 ns CL = 15 pF, CMOS signal levels 6
Propagation Delay Skew (Equal Temperature, Supplies) (3.3 V operation) tPSK2 12 ns CL = 15 pF, CMOS signal levels 6
Common-Mode Transient Immunity at Logic Low/High Output (3.3 V operation) /CML/, /CMH/ 25 35 kV/µs VI = 0 V or VDD1, VCM = 1000 V, transient magnitude = 800 V 6
IC Junction-to-Case Thermal Resistance, Side 1 θJCI 46 °C/W Thermocouple located at center of package underside 10
IC Junction-to-Case Thermal Resistance, Side 2 θJCO 41 °C/W 10
Operating Temperature (ADuM1100AR) TA -40 105 °C 11
Supply Voltages VDD1, VDD2 3 5.5 V All voltages relative to their respective ground 11
Logic High Input Voltage, 5 V Operation VIH 2 V 5 V operation (See Figure 11 and Figure 12) 11
Logic Low Input Voltage, 5 V Operation VIL 0 0.8 V 5 V operation (See Figure 11 and Figure 12) 11
Logic High Input Voltage, 3.3 V Operation VIH 1.5 V 3.3 V operation (See Figure 11 and Figure 12) 11
Logic Low Input Voltage, 3.3 V Operation VIL 0 0.5 V 3.3 V operation (See Figure 11 and Figure 12) 11
Input Signal Rise and Fall Times 1 ms 11
Storage Temperature TST -55 150 °C 12
Ambient Operating Temperature TA -40 125 °C 12
Supply Voltages VDD1, VDD2 -0.5 6.5 V All voltages relative to their respective ground 12
Input Voltage (max printed as VDD1 + 0.5) VI -0.5 V 12
Output Voltage (max printed as VDD2 + 0.5) VO -0.5 V 12
Average Current, per Pin -25 25 mA Temperature ≤ 105°C 12
Input Current -7 7 mA Temperature ≤ 125°C 12
Output Current -20 20 mA Temperature ≤ 125°C 12
Common-Mode Transients -100 100 kV/µs 12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing Abs Changes to Insulation Characteristics Section..............................6 Changes to Absolute Maximum Ratings........................................7 3

CAD (KiCad official)

  • Symbol: ADUM1100ARZ-RL7
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: adum1100arz-rl7-etched.step / adum1100arz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum1100arz-rl7.step / adum1100arz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (20 pp, sha256 d9e977acbe03330e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF