component
TPS6521825RSLR
Public Made by Adomby adom
Texas Instruments Power Management - Specialized, VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownTPS6521825RSLR
Texas Instruments · Power Management - Specialized · VQFN-48-EP(6x6)
TPS6521825RSLR from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN_DCDC1 | power_in | Input supply pin for DCDC1. |
| 2 | SDA | bidirectional | Data line for the I2C interface; connect to a pullup resistor. |
| 3 | SCL | input | Clock input for the I2C interface; connect to a pullup resistor. |
| 4 | LDO1 | power_out | Output voltage pin for LDO1; connect to a capacitor. |
| 5 | IN_LDO1 | power_in | Input supply pin for LDO1. |
| 6 | IN_LS3 | power_in | Input supply pin for load switch 3. |
| 7 | LS3 | power_out | Output voltage pin for load switch 3; connect to a capacitor. |
| 8 | PGOOD | output | Power-good output, open drain; pulled low when DCDC1-4 or LDO1 are out of regulation, and load switches and DCDC5-6 do not affect it. |
| 9 | AC_DET | input | AC monitor input and enable for DCDC1-4, LDO1 and load switches; tie to IN_BIAS if not used. |
| 10 | nPFO | output | Deglitched power-fail comparator output, open drain; pulled low when the PFI input is below the power-fail threshold. |
| 11 | GPIO1 | bidirectional | Configurable as DDR reset input (driving GPO2) or as a general-purpose open-drain output. |
| 12 | IN_DCDC4 | power_in | Input supply pin for DCDC4. |
| 13 | L4A | power_out | Switch pin for DCDC4; connect to inductor. |
| 14 | L4B | power_out | Switch pin for DCDC4; connect to inductor. |
| 15 | DCDC4 | power_out | Output voltage pin for DCDC4; connect to a capacitor. |
| 16 | PFI | input | Power-fail comparator input; connect to a resistor divider. |
| 17 | DC34_SEL | input | Power-up default selection pin for DCDC3 or DCDC4, programmed by a resistor to ground (resistor options in section 8.3.1.13). |
| 18 | IN_nCC | output | Push-pull output indicating whether DCDC5 and DCDC6 are powered from IN_BU (high) or the coin cell CC (low). |
| 19 | PGOOD_BU | output | Push-pull power-good output for DCDC5 and DCDC6; low when either is out of regulation, and high (at DCDC6 output voltage) when both are in regulation. |
| 20 | L5 | power_out | Switch pin for DCDC5; connect to inductor. |
| 21 | FB5 | input | Feedback voltage pin for DCDC5; connect to output capacitor. |
| 22 | FB6 | input | Feedback voltage pin for DCDC6; connect to output capacitor. |
| 23 | L6 | power_out | Switch pin for DCDC6; connect to inductor. |
| 24 | SYS_BU | power_out | System voltage pin for the battery-backup supply path; connect to a 1-µF capacitor, and connecting any external load is not recommended. |
| 25 | CC | power_in | Coin-cell battery input that supplies DCDC5 and DCDC6 when no voltage is applied to IN_BU; tie to ground if not in use. |
| 26 | GPIO3 | bidirectional | Configurable as warm reset (negative edge) for DCDC1 and DCDC2, or as a general-purpose open-drain output. |
| 27 | IN_BU | power_in | Default input supply pin for the battery-backup supplies (DCDC5 and DCDC6). |
| 28 | N/C | unconnected | No connect; leave pin floating. |
| 29 | N/C | unconnected | No connect; leave pin floating. |
| 30 | LS1 | power_out | Output voltage pin for load switch 1; connect to a capacitor. |
| 31 | IN_LS1 | power_in | Input supply pin for load switch 1. |
| 32 | IN_LS2 | power_in | Input supply pin for load switch 2. |
| 33 | LS2 | power_out | Output voltage pin for load switch 2; connect to a capacitor. |
| 34 | GPO2 | output | DDR reset signal controlled by GPIO1, or a general-purpose output; buffer configurable as push-pull or open drain, with 6 mA source/sink limit. |
| 35 | INT_LDO | power_out | Internal bias voltage; connect to a 1-µF capacitor, and TI does not recommend connecting any external load. |
| 36 | IN_BIAS | power_in | Input supply pin for the reference system. |
| 37 | IN_DCDC3 | power_in | Input supply pin for DCDC3. |
| 38 | L3 | power_out | Switch pin for DCDC3; connect to inductor. |
| 39 | FB3 | input | Feedback voltage pin for DCDC3; connect to output capacitor. |
| 40 | nWAKEUP | output | Signal to the SoC indicating a power-on event (active low, open-drain output). |
| 41 | FB2 | input | Feedback voltage pin for DCDC2; connect to output capacitor. |
| 42 | L2 | power_out | Switch pin for DCDC2; connect to inductor. |
| 43 | IN_DCDC2 | power_in | Input supply pin for DCDC2. |
| 44 | PB | input | Push-button monitor input, typically a momentary switch to ground (active low). |
| 45 | nINT | output | Interrupt output (active low, open drain); pulled low when an interrupt bit is set and released after the bit is read. |
| 46 | PWR_EN | input | Power-enable input for DCDC1-4, LDO1 and load switches. |
| 47 | FB1 | input | Feedback voltage pin for DCDC1; connect to output capacitor. |
| 48 | L1 | power_out | Switch pin for DCDC1; connect to inductor. |
| 49 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(6x6) |
| Category | Power Management (PMIC) |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
TPS6521825RSLR - Footprint:
Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm - 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps6521825rslr-etched.step/tps6521825rslr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps6521825rslr.step/tps6521825rslr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (94 pp, sha256
d04b48faa7750415, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).