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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

CBM706TAS8

Corebai Microelectronics · Supervisor And Reset ICs · SOIC-8

CBM706TAS8 from Corebai Microelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MR	input	Active-low manual reset input: pulling it below 0.6 V starts a reset, it is internally debounced, can be driven by TTL/CMOS logic or a switch, and is held high internally when floating.
2	VCC	power_in	Supply voltage input; a 0.1 µF decoupling capacitor should be placed between VCC and GND.
3	GND	power_in	Ground reference for all signals (0 V).
4	PFI	input	Power-fail comparator input compared against an internal 1.25 V reference; when PFI falls below 1.25 V, PFO is driven low.
5	PFO	output	Active-low power-fail output from the power-fail comparator, pulled low when PFI is below 1.25 V.
6	WDI	input	Watchdog input: a high-to-low or low-to-high transition must occur within the 1.6 s timeout, otherwise WDO is driven low, and each transition resets the internal timer.
7	RESET	output	Active-low reset output that is asserted when VCC falls below the reset threshold or MR is pulled low, and held low for 200 ms after the condition clears.
8	WDO	output	Active-low watchdog output that goes low on watchdog timeout and stays low while VCC is below the reset threshold, returning high immediately once VCC exceeds it.

Key specifications

Parameter	Value
Manufacturer	Corebai Microelectronics
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage range		1		5.5	V		4
Supply current			100	200	μA	VCC < 3.6 V	4
Supply current				150	μA	VCC < 5.5 V	4
Reset threshold (CBM706T)	VRST	3	3.08	3.15	V	CBM706T/CBM708T; VCC=3.15 V to 5.5 V	4
Delayed reset threshold			20		mV		4
Reset pulse width			200		ms	VCC = 3.3 V	4
Reset output voltage high	VOH	0.8			×VCC	VRST(max)<VCC<3.6V, ISOURCE=500μA	4
Reset output voltage low	VOL			0.3	V	VRST(max)<VCC<3.6V, ISINK=1.2mA	4
Reset output voltage high	VOH	-1.5			V	4.5V<VCC<5.5V, ISOURCE=800μA; printed as VCC−1.5V	4
Reset output voltage low	VOL			0.4	V	4.5V<VCC<5.5V, ISINK=3.2mA	4
Watchdog timeout period		1	1.6	2.25	sec	CBM706S/CBM706T: VCC=3.3V; VIL=0.4V, VIH=VCC×0.8 V	4
WDI pulse width		100			ns	VRST(max)<VCC<3.6 V	5
WDI pulse width		50			ns	4.5V<VCC<5.5 V	5
WDI input low voltage	VIL			0.6	V	VRST(max)<VCC<3.6V	5
WDI input high voltage	VIH	0.7			×VCC	VRST(max)<VCC<3.6V	5
WDI input low voltage	VIL			0.8	V	VCC=5.0V	5
WDI input high voltage	VIH	3.5			V	VCC=5.0V	5
WDI input current		-1	0.02	1	μA	WDI=0V or VCC	5
Watchdog output voltage high	VOH	0.8			×VCC	VRST(max)<VCC<3.6V, ISOURCE=500μA	5
Watchdog output voltage high	VOH	-1.5			V	4.5V<VCC<5.5V, ISOURCE=800μA; printed as VCC−1.5V	5
Watchdog output voltage low	VOL			0.3	V	VRST(max)<VCC<3.6V, ISINK=500μA	5
Watchdog output voltage low	VOL			0.6	V	4.5V<VCC<5.5V, ISINK=1.2mA	5
Manual reset input sink current		25	70	250	μA	MR=0V; VRST(max)<VCC<3.6V	5
Manual reset input sink current		100	250	600	μA	MR=0V; 4.5V<VCC<5.5V	5
Manual reset pulse width		500			ns	VRST(max)<VCC<3.6V	5
Manual reset pulse width		150			ns	4.5V<VCC<5.5V	5
MR input low voltage	VIL			0.6	V	VRST(max)<VCC<3.6V	5
MR input high voltage	VIH	0.7			×VCC	VRST(max)<VCC<3.6V	5
MR input low voltage	VIL			0.8	V	4.5V<VCC<5.5V	5
MR input high voltage	VIH	2			V	4.5V<VCC<5.5V	5
MR to reset output delay				750	ns	VRST(max)<VCC<3.6V	5
MR to reset output delay				250	ns	4.5V<VCC<5.5V	5
Power-fail input threshold		1.2	1.25	1.3	V	CBM706P/CBM706R/CBM708R, VCC=3V (printed row; same 1.25 V PFI threshold reference)	6
Power-fail input current	PFI	-25	0.01	25	nA	VCC=3.3V, PFI falling	6
Power-fail output voltage high	VOH	0.8			×VCC	VRST(max)<VCC<3.6V, ISOURCE=500μA	6
Power-fail output voltage low	VOL			0.3	V	VRST(max)<VCC<3.6V, ISINK=1.2mA	6
Power-fail output voltage high	VOH	-1.5			V	4.5V<VCC<5.5V, ISOURCE=800μA; printed as VCC−1.5V	6
Power-fail output voltage low	VOL			0.4	V	4.5V<VCC<5.5V, ISINK=3.2mA	6
Supply voltage (operating)	VCC	3.15		5.5	V	CBM70XT; TA = TMIN to TMAX	4
Voltage on all other inputs		-0.3			V	Printed as −0.3 V to VCC+0.3 V	5
ESD rating		4.5			kV	Printed as >4.5 kV	5

CAD (KiCad official)

Symbol: CBM706TAS8
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: cbm706tas8-etched.step / cbm706tas8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cbm706tas8.step / cbm706tas8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Corebai Microelectronics datasheet (23 pp, sha256 e9eda34860f7a1ba, retrieved 2026-10-18, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF