component
UCC28C54QDRQ1
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownUCC28C54QDRQ1
Texas Instruments · AC-DC Controllers And Regulators · SOIC-8
UCC28C54QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier output for loop compensation that can source and sink current and is internally current-limited so forcing COMP to GND commands zero duty cycle, with a 10 mA maximum error amplifier sink current and analog input range of -0.3 V to 6.3 V. |
| 2 | FB | input | Inverting input of the error amplifier, where the noninverting input is internally trimmed to 2.5 V ±1% and the analog input range is -0.3 V to 6.3 V. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator that terminates OUT conduction, has a typical gain of 3 V/V, and may need an RC filter against leading-edge noise. |
| 4 | RT/CT | bidirectional | Oscillator timing pin where a timing resistor from VREF and a timing capacitor to GND set fOSC, with TI recommending 1 kΩ to 100 kΩ and 220 pF to 4.7 nF; on the UCC28C54 the switching frequency is one-half of fOSC. |
| 5 | GND | power_in | Ground return for the output driver stage and the logic-level controller, and TI recommends keeping the signal return separate from the high-current gate driver path. |
| 6 | OUT | output | Totem-pole gate driver output that sources and sinks up to 1 A peak and is held low when VDD is below turn-on; on the UCC28C54 it runs at one-half the oscillator frequency due to an internal T flip-flop, limiting duty cycle to below 50%. |
| 7 | VDD | power_in | Analog controller bias supply with a 30 V absolute maximum and 30 mA maximum input current, requiring a 0.1 µF bypass to GND placed directly at the pin plus added capacitance at least 10 times the main switching FET gate capacitance and 10 times the VREF bypass capacitance. |
| 8 | VREF | power_out | 5-V reference output that supplies the oscillator timing charging current, requires a minimum 0.1 µF ceramic bypass to GND placed as close to the pin as possible, and must not have any higher external voltage superimposed on it, with an absolute maximum of 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
UCC28C54QDRQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc28c54qdrq1-etched.step/ucc28c54qdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc28c54qdrq1.step/ucc28c54qdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (54 pp, sha256
17e157e3c78ffd7e, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).