component
CY8C4014PVI-422T
Public Made by Adomby adom
Cypress Semicon CYPRESS, SSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCY8C4014PVI-422T
Cypress Semicon · CYPRESS · SSOP-28
CY8C4014PVI-422T from Cypress Semicon, in a SSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.5 | bidirectional | Port 0 GPIO that can also serve as a CSD sense or shield pin on AMUXBUS A or B. |
| 2 | P0.6 | bidirectional | Port 0 GPIO that can also serve as a CSD sense or shield pin on AMUXBUS A or B. |
| 3 | P0.7 | bidirectional | Port 0 GPIO that can also serve as a CSD sense or shield pin on AMUXBUS A or B. |
| 4 | P1.0 | bidirectional | Port 1 GPIO that can also serve as a CSD sense or shield pin on AMUXBUS A or B. |
| 5 | P1.1/OUT0 | bidirectional | Port 1 GPIO multiplexed with TCPWM output OUT0 (PWM output 0). |
| 6 | P1.2/SCL | bidirectional | Port 1 GPIO multiplexed with the I2C clock line, implemented in open-drain mode and not overvoltage tolerant. |
| 7 | P1.3/SDA | bidirectional | Port 1 GPIO multiplexed with the I2C data line, implemented in open-drain mode and not overvoltage tolerant. |
| 8 | P1.4/UND0 | bidirectional | Port 1 GPIO multiplexed with TCPWM underflow output UND0. |
| 9 | P1.5/OVF0 | bidirectional | Port 1 GPIO multiplexed with TCPWM overflow output OVF0. |
| 10 | P1.6/OVF0/UND0/nOUT0/CMPO_0 | bidirectional | Port 1 GPIO multiplexed with TCPWM outputs and the comparator output CMPO_0; it must not have a load to ground during POR and should be an output. |
| 11 | VSS | power_in | Ground pin. |
| 12 | NC | unconnected | No connect; this pin is not to be used and must be left floating. |
| 13 | P1.7/MATCH/EXT_CLK | bidirectional | Port 1 GPIO multiplexed with the match output MATCH and the external clock input EXT_CLK. |
| 14 | P2.0 | bidirectional | Port 2 GPIO that can also serve as a CSD sense or shield pin on AMUXBUS A or B. |
| 15 | VSS | power_in | Ground pin. |
| 16 | P3.0/SDA/SWD_IO | bidirectional | Port 3 GPIO multiplexed with the I2C data line and the SWD I/O line; Port 3 pins are not available for CapSense. |
| 17 | P3.1/SCL/SWD_CLK | bidirectional | Port 3 GPIO multiplexed with the I2C clock line and the SWD clock line; Port 3 pins are not available for CapSense. |
| 18 | P3.2 | bidirectional | Port 3 GPIO multiplexed with TCPWM output OUT0 (PWM output 0); Port 3 pins are not available for CapSense. |
| 19 | XRES | input | External reset input. |
| 20 | VSS | power_in | Ground pin. |
| 21 | P0.0/TRIN0 | bidirectional | Port 0 GPIO multiplexed with TCPWM trigger input TRIN0 and usable as a CSD sense or shield pin. |
| 22 | P0.1/TRIN1/CMPO_0 | bidirectional | Port 0 GPIO multiplexed with TCPWM trigger input TRIN1 and the sense comparator output CMPO_0. |
| 23 | P0.2/TRIN2 | bidirectional | Port 0 GPIO multiplexed with TCPWM trigger input TRIN2. |
| 24 | P0.3/TRIN3 | bidirectional | Port 0 GPIO multiplexed with TCPWM trigger input TRIN3. |
| 25 | P0.4/TRIN4/CMPO_0/EXT_CLK | bidirectional | Port 0 GPIO multiplexed with TCPWM trigger input TRIN4, the comparator output CMPO_0, and the external clock; it also serves as the CMOD capacitor connection. |
| 26 | VCCD | power_out | Regulated digital supply of 1.8 V ±5% that must be bypassed to ground with a 0.1 µF X5R capacitor in unregulated supply mode. |
| 27 | VDD | power_in | Power supply for both analog and digital sections, 1.71 V to 5.5 V. |
| 28 | VSS | power_in | Ground pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | SSOP-28 |
| Category | Embedded Processors & Controllers |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Digital supply relative to VSS | VDD_ABS | -0.5 | 6 | V | Digital supply relative to VSS | 14 | |
| Direct digital core voltage input relative to VSS | VCCD_ABS | -0.5 | 1.95 | V | Direct digital core voltage input relative to VSS | 14 | |
| Maximum current per GPIO | IGPIO_ABS | -25 | 25 | mA | 14 | ||
| GPIO injection current, Max for VIH > VDD, and Min for VIL < VSS | IGPIO_injection | -0.5 | 0.5 | mA | Current injected per pin | 14 | |
| Electrostatic discharge human body model | ESD_HBM | 2200 | V | 14 | |||
| Electrostatic discharge charged device model | ESD_CDM | 500 | V | 14 | |||
| Pin current for latch-up | LU | -140 | 140 | mA | Pin current for latch-up | 14 | |
| Power supply input voltage | VDD | 1.8 | 5.5 | V | With regulator enabled | 14 | |
| Power supply input voltage (VCCD = VDD) | VDD | 1.71 | 1.89 | V | Internally unregulated supply | 14 | |
| VDDIO domain supply | VDDIO | 1.71 | V | 14 | |||
| Execute from flash; CPU at 6 MHz | IDD5 | 2 | 2.85 | mA | Execute from flash; CPU at 6 MHz | 14 | |
| Execute from flash; CPU at 12 MHz | IDD8 | 3.2 | 3.75 | mA | Execute from flash; CPU at 12 MHz | 14 | |
| Execute from flash; CPU at 16 MHz | IDD11 | 4 | 4.5 | mA | Execute from flash; CPU at 16 MHz | 14 | |
| I2C wakeup, WDT on. 6 MHz | IDD20 | 1.1 | mA | I2C wakeup, WDT on. 6 MHz | 14 | ||
| I2C wakeup, WDT on. 12 MHz | IDD20A | 1.4 | mA | I2C wakeup, WDT on. 12 MHz | 14 | ||
| I2C wakeup and WDT on | IDD26 | 2.5 | 8.2 | µA | I2C wakeup and WDT on | 14 | |
| I2C wakeup and WDT on | IDD29 | 2.5 | 12 | µA | I2C wakeup and WDT on | 15 | |
| I2C wakeup and WDT on | IDD32 | 2.5 | 9.2 | µA | I2C wakeup and WDT on | 15 | |
| Supply current while XRES asserted | IDD_XR | 2 | 5 | mA | Supply current while XRES asserted | 14 | |
| CPU frequency | FCPU | 16 | MHz | 1.71 VDD 5.5 | 15 | ||
| Input voltage high threshold, LVTTL input | VIH | 2 | V | LVTTL input, VDD >= 2.7 V | 15 | ||
| Input voltage low threshold, LVTTL input | VIL | 0.8 | V | LVTTL input, VDD >= 2.7 V | 15 | ||
| Pull-up resistor | RPULLUP | 3.5 | 5.6 | 8.5 | kΩ | 15 | |
| Pull-down resistor | RPULLDOWN | 3.5 | 5.6 | 8.5 | kΩ | 15 | |
| Input leakage current (absolute value) | IIL | 2 | nA | 25 °C, VDD = 3.0 V | 15 | ||
| Input capacitance | CIN | 3 | 7 | pF | 15 | ||
| Response Time High Bandwidth mode, 50-mV overdrive | TCOMP1 | 90 | ns | High Bandwidth mode, 50-mV overdrive | 18 | ||
| Response Time Low Power mode, 50-mV overdrive | TCOMP2 | 110 | ns | Low Power mode, 50-mV overdrive | 18 | ||
| Max allowed ripple on power supply, DC to 10 MHz | VDD_RIPPLE | -50 | 50 | mV | VDD > 2V (with ripple), 25 °C TA, Sensitivity = 0.1 pF | 18 | |
| Reference Buffer Output | VREFHI | 1.1 | 1.2 | 1.3 | V | 18 | |
| IDAC1 (8-bits) block current | IDAC1IDD | 1125 | µA | 18 | |||
| IDAC2 (7-bits) block current | IDAC2IDD | 1125 | µA | 18 | |||
| Voltage range of operation | VCSD | 1.71 | 5.5 | V | 1.8 V ±5% or 1.8 V to 5.5 V | 18 | |
| Voltage compliance range of IDAC | VCOMPIDAC | 0.8 | V | 18 | |||
| DNL for 8-bit resolution | IDAC1DNL | -1 | 1 | LSB | 18 | ||
| INL for 8-bit resolution | IDAC1INL | -3 | 3 | LSB | 18 | ||
| DNL for 7-bit resolution | IDAC2DNL | -1 | 1 | LSB | 18 | ||
| INL for 7-bit resolution | IDAC2INL | -3 | 3 | LSB | 18 | ||
| Ratio of counts of finger to noise. Guaranteed by characterization | SNR | 5 | Ratio | Capacitance range of 9 to 35 pF, 0.1 pF sensitivity | 18 | ||
| All zeroes input | IDACOFFSET | -1 | 1 | LSB | All zeroes input | 18 | |
| Full-scale error less offset | IDACGAIN | -10 | 10 | % | Full-scale error less offset | 18 | |
| Settling time to 0.5 LSB for 8-bit IDAC | IDACSET8 | 10 | µs | Full-scale transition. No external load. | 18 | ||
| ADC resolution | ADCRes | 1 | mV | 19 | |||
| ADC gain error | ADCError | 1 | % | For 0 to 5-V range, 0.1% accurate Rin / Rbleed,1% accurate Internal Vref and Temp range of 0 to 70 °C | 19 | ||
| ADC integral non-linearity | ADCINL | 18 | mV | 0 to 5-V input and 0 to 70 °C | 19 | ||
| ADC Sample rate | ADCSamp | 58 | sps | 19 | |||
| Block current consumption at 3 MHz | ITCPWM1 | 45 | µA | All modes (TCPWM) | 20 | ||
| Block current consumption at 8 MHz | ITCPWM2 | 145 | µA | All modes (TCPWM) | 20 | ||
| Block current consumption at 100 kHz | II2C1 | 25 | µA | 20 | |||
| Block current consumption at 400 kHz | II2C2 | 135 | µA | 20 | |||
| I2C enabled in Deep Sleep mode | ISBI2C | 2.5 | µA | 20 | |||
| Bit rate | FI2C1 | 400 | Kbps | 20 | |||
| External clock input frequency | ExtClkFreq | 0 | 16 | MHz | 23 | ||
| Duty cycle; measured at VDD/2 | ExtClkDuty | 45 | 55 | % | Duty cycle; measured at VDD/2 | 23 | |
| Operating ambient temperature | TA | -40 | 25 | 85 | °C | 26 | |
| Operating junction temperature | TJ | -40 | 100 | °C | 26 | ||
| Package θJA (28-pin SSOP) | TJA | 66.6 | °C/Watt | 26 | |||
| Package θJC (28-pin SSOP) | TJC | 34 | °C/Watt | 26 | |||
| Wakeup from Deep Sleep mode | TDEEPSLEEP | 35 | µs | 15 | |||
| External modulator capacitor | CMOD | 2.2 | nF | 5-V rating, X7R or NP0 cap. | 19 |
CAD (KiCad official)
- Symbol:
CY8C4014PVI-422T - Footprint:
Package_SO:SSOP-28_5.3x10.2mm_P0.65mm - 3D model: SSOP-28 (KiCad packages3D, STEP)
- 3D model files:
cy8c4014pvi-422t-etched.step/cy8c4014pvi-422t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy8c4014pvi-422t.step/cy8c4014pvi-422t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Cypress Semicon datasheet (36 pp, sha256
6c7edf8ac0f0328f, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).