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SN74AC74DR

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Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74AC74DR

Texas Instruments · Flip Flops · SOIC-14

SN74AC74DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1 CLR input Channel 1 Clear input (active low); asynchronous reset that forces 1Q to low when held low, independent of clock input.
2 1D input Channel 1 Data input; state sampled on rising clock edge, requires minimum 3 ns setup time before clock transition.
3 1CLK input Channel 1 Clock input; positive edge triggered, captures 1D state on rising clock edge with max 10 ns propagation delay.
4 1 PRE input Channel 1 Preset input (active low); asynchronous set that forces 1Q to high when held low, independent of clock input.
5 1Q output Channel 1 non-inverted Q output; logical state of flip-flop that can source/sink ±24 mA at 4.5V supply.
6 1 Q output Channel 1 inverted Q output (Q-bar complement); logical inverse of 1Q that can source/sink ±24 mA at 4.5V supply.
7 GND power_in Ground reference potential (0V); required current return path for all logic circuits and output drivers.
8 2 Q output Channel 2 inverted Q output (Q-bar complement); logical inverse of 2Q that can source/sink ±24 mA at 4.5V supply.
9 2Q output Channel 2 non-inverted Q output; logical state of flip-flop that can source/sink ±24 mA at 4.5V supply.
10 2 PRE input Channel 2 Preset input (active low); asynchronous set that forces 2Q to high when held low, independent of clock input.
11 2CLK input Channel 2 Clock input; positive edge triggered, captures 2D state on rising clock edge with max 10 ns propagation delay.
12 2D input Channel 2 Data input; state sampled on rising clock edge, requires minimum 3 ns setup time before clock transition.
13 2 CLR input Channel 2 Clear input (active low); asynchronous reset that forces 2Q to low when held low, independent of clock input.
14 VCC power_in Positive supply voltage (2V to 6V range); requires 0.1 µF bypass capacitor per power supply recommendations section 8.3.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74AC74DR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ac74dr-etched.step / sn74ac74dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ac74dr.step / sn74ac74dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 be2357defe00c911, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF