component

CD74HC73M

Public Made by Adom

by adom

lingxingic Flip Flops, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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CD74HC73M

lingxingic · Flip Flops · SOP-14

CD74HC73M from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CP input Clock input for flip-flop 1, triggered on the HIGH-to-LOW (negative) clock edge.
2 1R input Asynchronous reset input for flip-flop 1, active LOW; a LOW level forces 1Q LOW and 1Q HIGH regardless of the clock.
3 1K input Synchronous K input for flip-flop 1, sampled at the HIGH-to-LOW clock transition.
4 VCC power_in Supply voltage: 2.0 V to 6.0 V for CD74HC73, 4.5 V to 5.5 V for CD74HCT73.
5 2CP input Clock input for flip-flop 2, triggered on the HIGH-to-LOW (negative) clock edge.
6 2R input Asynchronous reset input for flip-flop 2, active LOW; a LOW level forces 2Q LOW and 2Q HIGH regardless of the clock.
7 2J input Synchronous J input for flip-flop 2, sampled at the HIGH-to-LOW clock transition.
8 2Q output Complement output of flip-flop 2 (printed as 2Q with overbar; overbar lost in text extraction).
9 2Q output True output of flip-flop 2.
10 2K input Synchronous K input for flip-flop 2, sampled at the HIGH-to-LOW clock transition.
11 GND power_in Ground reference (0 V).
12 1Q output True output of flip-flop 1.
13 1Q output Complement output of flip-flop 1 (printed as 1Q with overbar; overbar lost in text extraction).
14 1J input Synchronous J input for flip-flop 1, sampled at the HIGH-to-LOW clock transition.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 2 5 6 V CD74HC73 6
input voltage VI 0 V CD74HC73; max printed as VCC 6
output voltage VO 0 V CD74HC73; max printed as VCC 6
ambient temperature Tamb -40 125 ℃ CD74HC73 6
supply voltage VCC -0.5 7 V 6
supply current ICC 50 mA 6
ground current IGND -50 mA 6
input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 6
output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 6
output current IO -25 25 mA -0.5V < VO < VCC+0.5V 6
storage temperature Tstg -65 150 ℃ 6
soldering temperature TL 260 ℃ 10s, SOP/TSSOP 6
HIGH-level input voltage VIH 1.5 1.2 V VCC=2.0V; Tamb=-40℃ to +85℃ 7
HIGH-level input voltage VIH 3.15 2.4 V VCC=4.5V; Tamb=-40℃ to +85℃ 7
HIGH-level input voltage VIH 4.2 3.2 V VCC=6.0V; Tamb=-40℃ to +85℃ 7
LOW-level input voltage VIL 0.8 0.5 V VCC=2.0V; Tamb=-40℃ to +85℃ 7
LOW-level input voltage VIL 2.1 1.35 V VCC=4.5V; Tamb=-40℃ to +85℃ 7
LOW-level input voltage VIL 2.8 1.8 V VCC=6.0V; Tamb=-40℃ to +85℃ 7
HIGH-level output voltage VOH 1.9 2 V VCC=2.0V; IO=-20uA; Tamb=-40℃ to +85℃ 7
HIGH-level output voltage VOH 4.4 4.5 V VCC=4.5V; IO=-20uA; Tamb=-40℃ to +85℃ 7
HIGH-level output voltage VOH 5.9 6 V VCC=6.0V; IO=-20uA; Tamb=-40℃ to +85℃ 7
HIGH-level output voltage VOH 3.84 4.32 V VCC=4.5V; IO=-4.0mA; Tamb=-40℃ to +85℃ 7
HIGH-level output voltage VOH 5.34 5.81 V VCC=6.0V; IO=-5.2mA; Tamb=-40℃ to +85℃ 7
LOW-level output voltage VOL 0 0.1 V VCC=2.0V; IO=20uA; Tamb=-40℃ to +85℃ 7
LOW-level output voltage VOL 0.15 0.33 V VCC=4.5V; IO=4.0mA; Tamb=-40℃ to +85℃ 7
LOW-level output voltage VOL 0.16 0.33 V VCC=6.0V; IO=5.2mA; Tamb=-40℃ to +85℃ 7
input leakage current II -1 1 uA VCC=6.0V; VI=VCC or GND; Tamb=-40℃ to +85℃ 7
supply current ICC 80 uA VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40℃ to +85℃ 7
HIGH-level input voltage VIH 1.5 V VCC=2.0V; Tamb=-40℃ to +125℃ 8
HIGH-level input voltage VIH 3.15 V VCC=4.5V; Tamb=-40℃ to +125℃ 8
HIGH-level input voltage VIH 4.2 V VCC=6.0V; Tamb=-40℃ to +125℃ 8
LOW-level input voltage VIL 0.5 V VCC=2.0V; Tamb=-40℃ to +125℃ 8
LOW-level input voltage VIL 1.35 V VCC=4.5V; Tamb=-40℃ to +125℃ 8
LOW-level input voltage VIL 1.8 V VCC=6.0V; Tamb=-40℃ to +125℃ 8
HIGH-level output voltage VOH 1.9 V VCC=2.0V; IO=-20uA; Tamb=-40℃ to +125℃ 8
HIGH-level output voltage VOH 4.4 V VCC=4.5V; IO=-20uA; Tamb=-40℃ to +125℃ 8
HIGH-level output voltage VOH 5.9 V VCC=6.0V; IO=-20uA; Tamb=-40℃ to +125℃ 8
HIGH-level output voltage VOH 3.7 V VCC=4.5V; IO=-4.0mA; Tamb=-40℃ to +125℃ 8
HIGH-level output voltage VOH 5.2 V VCC=6.0V; IO=-5.2mA; Tamb=-40℃ to +125℃ 8
LOW-level output voltage VOL 0.1 V VCC=2.0V; IO=20uA; Tamb=-40℃ to +125℃ 8
LOW-level output voltage VOL 0.4 V VCC=4.5V; IO=4.0mA; Tamb=-40℃ to +125℃ 8
input leakage current II -1 1 uA VCC=6.0V; VI=VCC or GND; Tamb=-40℃ to +125℃ 8
supply current ICC 160 uA VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40℃ to +125℃ 8
nCP to nQ propagation delay tPLH, tPHL 52 160 ns VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ 9
nCP to nQ propagation delay tPLH, tPHL 19 32 ns VCC=4.5V; CL=50pF; Tamb=-40℃ to +85℃ 9
nCP to nQ propagation delay tPLH, tPHL 15 27 ns VCC=6.0V; CL=50pF; Tamb=-40℃ to +85℃ 9
nCP pulse width HIGH or LOW tw 100 22 ns VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ 9
nCP pulse width HIGH or LOW tw 20 8 ns VCC=4.5V; CL=50pF; Tamb=-40℃ to +85℃ 9
nCP pulse width HIGH or LOW tw 17 6 ns VCC=6.0V; CL=50pF; Tamb=-40℃ to +85℃ 9
nJ, nK to nCP set-up time tsu 125 22 ns VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ 9
nJ, nK to nCP set-up time tsu 25 8 ns VCC=4.5V; CL=50pF; Tamb=-40℃ to +85℃ 9
nJ, nK to nCP set-up time tsu 21 6 ns VCC=6.0V; CL=50pF; Tamb=-40℃ to +85℃ 9
maximum clock frequency fmax 4.8 30 MHz VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ 9
maximum clock frequency fmax 24 91 MHz VCC=4.5V; CL=50pF; Tamb=-40℃ to +85℃ 9
maximum clock frequency fmax 28 108 MHz VCC=6.0V; CL=50pF; Tamb=-40℃ to +85℃ 9

CAD (KiCad official)

  • Symbol: CD74HC73M
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd74hc73m-etched.step / cd74hc73m-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd74hc73m.step / cd74hc73m.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (17 pp, sha256 3d404d6b159fde46, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF