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LM98620VHB

Public Made by Adom

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Texas Instruments Video Interface ICs, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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LM98620VHB

Texas Instruments · Video Interface ICs · TQFP-80(12x12)

LM98620VHB from Texas Instruments, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SHD/HOLD input Data clamp pulse/hold input used for once-per-pixel sample timing.
2 VDDD power_in Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS.
3 VSSD power_in Digital power supply ground.
4 CLPIN input Input pulse that invokes the input clamp switch.
5 BLKCLP input Input pulse that invokes the black calibration loop, with an internal 108 kΩ pull-down to VSSD.
6 AGC_ONB input Input pulse that invokes the white calibration loop; pulse low to initiate white clamp (active low), tie high to disable, internal 108 kΩ pull-up to VDDD.
7 OVPB input Over-voltage protection enable (active low) that switches OS inputs to ground during power-up, to be tied high after AFE and CCD voltages have stabilized.
8 MCLK input Master clock input.
9 GPI1 input General-purpose input 1, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13).
10 GPI2 input General-purpose input 2, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13).
11 GPI3 input General-purpose input 3, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13).
12 GPI4 input General-purpose input 4, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13).
13 GPI5 input General-purpose input 5, mapped into LVDS output data (pin grouped as GPI1-5 on pins 9 to 13).
14 VSSD power_in Digital power supply ground.
15 VDDD power_in Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS.
16 IBIAS passive Optional IBIAS resistor connection; connect an 11 kΩ 1% resistor to VSSA to minimize device-to-device power variation.
17 VREG1 power_out Decoupling connection for VREG1, approx. 1.8 V output (voltage provided for debugging only, not guaranteed).
18 VSSD power_in Digital power supply ground.
19 VDDD power_in Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS.
20 VREG2 power_out Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed).
21 TXCLK1+ output Positive leg of differential LVDS output clock 1.
22 TXCLK1- output Negative leg of differential LVDS output clock 1.
23 TXOUTC1+ output Positive leg of differential LVDS output data C1.
24 TXOUTC1- output Negative leg of differential LVDS output data C1.
25 TXOUTB1+ output Positive leg of differential LVDS output data B1.
26 TXOUTB1- output Negative leg of differential LVDS output data B1.
27 VREG2 power_out Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed).
28 VSSLVDS power_in LVDS power supply ground.
29 TXOUTA1+ output Positive leg of differential LVDS output data A1.
30 TXOUTA1- output Negative leg of differential LVDS output data A1.
31 TXCLK2+ output Positive leg of differential LVDS output clock 2.
32 TXCLK2- output Negative leg of differential LVDS output clock 2.
33 VREG2 power_out Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed).
34 VSSLVDS power_in LVDS power supply ground.
35 TXOUTC2+ output Positive leg of differential LVDS output data C2.
36 TXOUTC2- output Negative leg of differential LVDS output data C2.
37 TXOUTB2+ output Positive leg of differential LVDS output data B2.
38 TXOUTB2- output Negative leg of differential LVDS output data B2.
39 TXOUTA2+ output Positive leg of differential LVDS output data A2.
40 TXOUTA2- output Negative leg of differential LVDS output data A2.
41 VSSLVDS power_in LVDS power supply ground.
42 VSSLVDS power_in LVDS power supply ground.
43 VREG2 power_out Decoupling connection for VREG2, approx. 1.8 V output (voltage provided for debugging only, not guaranteed).
44 VDDLVDS power_in LVDS power supply, 3.0 V to 3.6 V, which must not exceed VDDD.
45 VDDLVDS power_in LVDS power supply, 3.0 V to 3.6 V, which must not exceed VDDD.
46 VREG1 power_out Decoupling connection for VREG1, approx. 1.8 V output (voltage provided for debugging only, not guaranteed).
47 TESTO_1 output Digital test output.
48 TESTO_0 output Digital test output.
49 RESETB input Master reset input, active low, with an internal 108 kΩ pull-up to VDDD.
50 SCLK input Serial clock for the 4-wire serial interface.
51 SDI input Serial data input for the 4-wire serial interface.
52 SENB input Serial enable for the 4-wire serial interface, active low, with an internal 108 kΩ pull-up to VDDD.
53 SDO output Serial output data for the 4-wire serial interface.
54 VDDD power_in Digital power supply, 3.0 V to 3.6 V, which must be at or slightly above VDDA and VDDLVDS.
55 VSSD power_in Digital power supply ground.
56 VSSA power_in Analog power supply ground.
57 VREF power_in Reference voltage bypass, approx. 1.2 V output (voltage provided for debugging only, not guaranteed).
58 VDDA power_in Analog power supply, 3.0 V to 3.6 V.
59 VREFTOUT output Top reference bypass, approx. 2.23 V output; connect to bypass capacitors and VREFTINx (voltage provided for debugging only, not guaranteed).
60 VREFBOUT output Bottom reference bypass, approx. 0.98 V output; connect to bypass capacitors and VREFBINx (voltage provided for debugging only, not guaranteed).
61 VREFBIN2 input Bottom reference input voltage for the ADC; connect to VREFBOUT.
62 VREFTIN2 input Top reference input voltage for the ADC; connect to VREFTOUT.
63 VREFBIN1 input Bottom reference input voltage for the AFE; connect to VREFBOUT.
64 VREFTIN1 input Top reference input voltage for the AFE; connect to VREFTOUT.
65 VSSA power_in Analog power supply ground.
66 OSR1 input Input voltage 1 for the red channel.
67 VDDA power_in Analog power supply, 3.0 V to 3.6 V.
68 OSR2 input Input voltage 2 for the red channel.
69 VSSA power_in Analog power supply ground.
70 OSG1 input Input voltage 1 for the green channel.
71 VDDA power_in Analog power supply, 3.0 V to 3.6 V.
72 OSG2 input Input voltage 2 for the green channel.
73 VSSA power_in Analog power supply ground.
74 OSB1 input Input voltage 1 for the blue channel.
75 VDDA power_in Analog power supply, 3.0 V to 3.6 V.
76 OSB2 input Input voltage 2 for the blue channel.
77 VSSA power_in Analog power supply ground.
78 VCLP_EXT input External clamp voltage; connect to VCLP_INT or a customer-supplied reference voltage.
79 VCLP_INT output Internally generated V-clamp voltage, approx. 1.65 V output; connect to bypass capacitors and VCLP_EXT (voltage provided for debugging only, not guaranteed).
80 SHP/SAMPLE input Pedestal clamp pulse/sample input used for once-per-pixel sample timing.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-80(12x12)
Category Interface
Pins 80

CAD (KiCad official)

  • Symbol: LM98620VHB
  • Footprint: Package_QFP:TQFP-80_12x12mm_P0.5mm
  • 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: lm98620vhb-etched.step / lm98620vhb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm98620vhb.step / lm98620vhb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (71 pp, sha256 e6098b8fe4d2438f, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF