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LT8390EFE#PBF
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Analog Devices DC-DC Controllers, TSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownLT8390EFE#PBF
Analog Devices · DC-DC Controllers · TSSOP-28-EP
LT8390EFE#PBF from Analog Devices, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BG1 | output | Buck side bottom gate drive for the buck side bottom N-channel MOSFET, swinging from ground to INTVCC. |
| 2 | BST1 | passive | Buck side bootstrap floating driver supply with integrated Schottky diode from INTVCC, needs an external capacitor to SW1 and swings from a diode drop below INTVCC to (VIN + INTVCC). |
| 3 | SW1 | passive | Buck side switch node that swings from a Schottky diode voltage drop below ground up to VIN. |
| 4 | TG1 | output | Buck side top gate drive for the top N-channel MOSFET, swinging from SW1 to BST1. |
| 5 | LSP | input | Positive terminal of the buck side inductor current sense resistor (RSENSE); use a Kelvin connection. |
| 6 | LSN | input | Negative terminal of the buck side inductor current sense resistor (RSENSE); use a Kelvin connection. |
| 7 | VIN | power_in | Input supply (4V to 60V) that must be tied to the power input to determine buck, buck-boost or boost region, bypassed to ground with at least 1µF ceramic. |
| 8 | INTVCC | power_out | Internal 5V linear regulator output supplied from VIN that powers control circuitry and gate drivers, bypassed to ground with at least 4.7µF ceramic. |
| 9 | EN/UVLO | input | Enable and undervoltage lockout input; below 0.3V shuts down the part, above 1.233V enables, 1.220V falling threshold with 2.5µA hysteresis current, tie to VIN if unused. |
| 10 | TEST | input | Factory test pin that must be connected directly to ground for the part to operate properly. |
| 11 | LOADEN | input | Load switch enable input controlling the high side PMOS load switch; tie to VREF or INTVCC if unused, and low turns off TG1/TG2 and LOADTG and turns on BG1/BG2. |
| 12 | VREF | power_out | Accurate 2V reference output capable of supplying 1mA, bypassed to ground with a 0.47µF ceramic capacitor. |
| 13 | CTRL | input | Control input for the ISP/ISN current sense threshold, 100mV full scale for VCTRL of 1.35V or more (tie to VREF), and below 0.3V stops switching. |
| 14 | ISP | input | Positive terminal of the ISP/ISN current sense resistor (RIS); use a Kelvin connection. |
| 15 | ISN | input | Negative terminal of the ISP/ISN current sense resistor (RIS); use a Kelvin connection. |
| 16 | ISMON | output | Current sense monitor output voltage equal to ten times V(ISP-ISN) plus 0.25V offset. |
| 17 | PGOOD | output | Power good open-drain output pulled low when FB is within ±10% of final regulation voltage, requiring an external pull-up resistor. |
| 18 | SS | passive | Soft-start timer pin with a capacitor to ground (0.1µF recommended) charged by 12.5µA, and a resistor to VREF selects hiccup (none), latch-off (499kΩ) or keep-running (100kΩ) fault mode. |
| 19 | FB | input | Voltage loop feedback input regulated to 1.00V, with short condition below 0.25V and overvoltage above 1.1V turning off all gate drives. |
| 20 | VC | passive | Error amplifier output setting the inductor current comparator threshold, compensated with an external RC network and disconnected from internal loads when LOADEN is low. |
| 21 | RT | passive | Switching frequency setting pin; a resistor to ground sets the oscillator from 150kHz to 650kHz. |
| 22 | SYNC/SPRD | input | Ground for internal oscillator frequency, apply a clock for external synchronization, or tie to INTVCC for ±15% triangle spread spectrum. |
| 23 | LOADTG | output | High side PMOS load switch gate drive, a buffered inverted LOADEN signal swinging from the higher of (VOUT-5V) and 1.2V to VOUT; leave unconnected if unused. |
| 24 | VOUT | power_in | Output supply pin tied to the power output to determine operation region and serving as positive rail for LOADTG drive, bypassed with at least 1µF ceramic. |
| 25 | TG2 | output | Boost side top gate drive for the top N-channel MOSFET, swinging from SW2 to BST2. |
| 26 | SW2 | passive | Boost side switch node that swings from a Schottky diode voltage drop below ground to VOUT. |
| 27 | BST2 | passive | Boost side bootstrap floating driver supply with integrated Schottky diode from INTVCC, needs an external capacitor to SW2 and swings from a diode drop below INTVCC to (VOUT + INTVCC). |
| 28 | BG2 | output | Boost side bottom gate drive for the bottom N-channel MOSFET, swinging from ground to INTVCC. |
| 29 | GND | power_in | Exposed pad ground that must be soldered directly to the ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-28-EP |
| Category | Power Management ICs |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN, EN/UVLO, VOUT, ISP, ISN | 60 | V | 2 | ||||
| (ISP-ISN) | V(ISP-ISN) | -1 | 1 | V | 2 | ||
| SW1, SW2, LSP, LSN | -6 | 60 | V | 2 | |||
| INTVCC, (BST1-SW1), (BST2-SW2) | 6 | V | 2 | ||||
| (BST1-LSP), (BST1-LSN) | 6 | V | 2 | ||||
| FB, LOADEN, SYNC/SPRD, CTRL, PGOOD | 6 | V | 2 | ||||
| Operating junction temperature range, LT8390E | TJ | -40 | 125 | °C | Notes 2, 3 | 2 | |
| Storage temperature range | TSTG | -65 | 150 | °C | 2 | ||
| VIN Operating Voltage Range | 4 | 60 | V | 3 | |||
| VOUT Voltage Range | 0 | 60 | V | 3 | |||
| INTVCC Regulation Voltage | 4.85 | 5 | 5.15 | V | IINTVCC = 20mA | 3 | |
| INTVCC Current Limit | 80 | 110 | 160 | mA | VINTVCC = 4.5V | 3 | |
| INTVCC Undervoltage Lockout Threshold Falling | 3.44 | 3.54 | 3.64 | V | Falling | 3 | |
| VREF Regulation Voltage | 1.97 | 2 | 2.03 | V | IVREF = 100µA | 3 | |
| VREF Current Limit | 2 | 2.5 | 3.2 | mA | VREF = 1.8V | 3 | |
| VREF Undervoltage Lockout Threshold Falling | 1.78 | 1.84 | 1.9 | V | Falling | 3 | |
| EN/UVLO Shutdown Threshold | 0.3 | 0.6 | 1 | V | 4 | ||
| EN/UVLO Enable Threshold Falling | 1.196 | 1.22 | 1.244 | V | Falling | 4 | |
| CTRL Input Bias Current | 0 | 20 | 50 | nA | VCTRL = 0.75V, Current Out of Pin | 4 | |
| CTRL Latch-Off Threshold Falling | 285 | 300 | 315 | mV | Falling | 4 | |
| LOADEN Threshold Rising | 1.3 | 1.4 | 1.5 | V | Rising | 4 | |
| LOADTG On Voltage | V(VOUT-LOADTG) | 4.6 | 5 | 5.6 | V | VOUT = 12V | 4 |
| LOADTG Off Voltage | V(VOUT-LOADTG) | -0.1 | 0 | 0.1 | V | VOUT = 12V | 4 |
| Full Scale Current Regulation | V(ISP-ISN) | 97 | 100 | 103 | mV | VCTRL = 2V, VISP = 12V | 4 |
| 1/10th Current Regulation | V(ISP-ISN) | 8 | 10 | 12 | mV | VCTRL = 0.35V, VISP = 12V | 4 |
| ISMON Monitor Output | VISMON | 1.2 | 1.25 | 1.3 | V | V(ISP-ISN) = 100mV, VISP = 12V/0V | 4 |
| ISMON Monitor Output | VISMON | 0.3 | 0.35 | 0.4 | V | V(ISP-ISN) = 10mV, VISP = 12V/0V | 4 |
| ISMON Monitor Output | VISMON | 0.2 | 0.25 | 0.3 | V | V(ISP-ISN) = 0mV, VISP = 12V/0V | 4 |
| ISP/ISN Input Common Mode Range | 0 | 60 | V | 4 | |||
| FB Regulation Voltage | 0.985 | 1 | 1.015 | V | VC = 1.2V | 4 | |
| VC Standby Leakage Current | -10 | 0 | 10 | nA | VC = 1.2V, VLOADEN = 0V | 4 | |
| Maximum Current Sense Threshold, Buck | V(LSP-LSN) | 35 | 50 | 65 | mV | Buck, VFB = 0.8V | 5 |
| Maximum Current Sense Threshold, Boost | V(LSP-LSN) | 40 | 50 | 60 | mV | Boost, VFB = 0.8V | 5 |
| FB Overvoltage Threshold Rising | VFB | 1.08 | 1.1 | 1.12 | V | Rising | 5 |
| FB Overvoltage Hysteresis | 35 | 50 | 65 | mV | 5 | ||
| FB Short Threshold Falling | VFB | 0.24 | 0.25 | 0.26 | V | Falling | 5 |
| FB Short Hysteresis | 35 | 50 | 65 | mV | Hysteresis | 5 | |
| PGOOD Upper Threshold Offset from VFB Rising | 8 | 10 | 12 | % | Rising | 5 | |
| PGOOD Lower Threshold Offset from VFB Falling | -12 | -10 | -8 | % | Falling | 5 | |
| SS Pull-Up Current | 10.5 | 12.5 | 14.5 | µA | VFB = 0.4V, VSS = 0V | 5 | |
| SS Pull-Down Current | 1.05 | 1.25 | 1.45 | µA | VFB = 0.1V, VSS = 2V | 5 | |
| Switching Frequency | 190 | 200 | 210 | kHz | VSYNC/SPRD = 0V, RT = 226kΩ | 5 | |
| Switching Frequency | 380 | 400 | 420 | kHz | VSYNC/SPRD = 0V, RT = 100kΩ | 5 | |
| Switching Frequency | 570 | 600 | 630 | kHz | VSYNC/SPRD = 0V, RT = 59.0kΩ | 5 | |
| SYNC Frequency | 150 | 650 | kHz | 5 | |||
| SYNC/SPRD Input Bias Current | -0.1 | 0 | 0.1 | µA | VSYNC/SPRD = 5V | 5 | |
| Highest Spread Spectrum Above Oscillator Frequency | 12.5 | 14.5 | 16.5 | % | VSYNC/SPRD = 5V | 5 | |
| Lowest Spread Spectrum Below Oscillator Frequency | -17.7 | -15.7 | -13.7 | % | VSYNC/SPRD = 5V | 5 | |
| Buck-Boost to Boost (VIN/VOUT) | 0.73 | 0.75 | 0.77 | 5 | |||
| Boost to Buck-Boost (VIN/VOUT) | 0.83 | 0.85 | 0.87 | 5 | |||
| Buck to Buck-Boost (VIN/VOUT) | 1.16 | 1.18 | 1.2 | 5 | |||
| Buck-Boost to Buck (VIN/VOUT) | 1.31 | 1.33 | 1.35 | 5 | |||
| Peak-Buck to Peak-Boost (VIN/VOUT) | 0.96 | 0.98 | 1 | 5 | |||
| Peak-Boost to Peak-Buck (VIN/VOUT) | 1 | 1.02 | 1.04 | 5 | |||
| Thermal resistance, junction-to-ambient | θJA | 30 | °C/W | FE package, 28-lead plastic TSSOP | 2 | ||
| Thermal resistance, junction-to-case | θJC | 5 | °C/W | FE package, 28-lead plastic TSSOP | 2 |
CAD (KiCad official)
- Symbol:
LT8390EFE#PBF - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: TSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files:
lt8390efe-pbf-etched.step/lt8390efe-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt8390efe-pbf.step/lt8390efe-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
bedb46ecab867bbe, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).