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Contents

README

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S-LP2309LT1G

LRC · MOSFETs · SOT-23

S-LP2309LT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Gate terminal of the P-channel MOSFET, with gate-to-source voltage limited to ±20 V and threshold VGS(th) of -1 V min to -3 V max at ID = -250 µA.
2 Source passive Source terminal of the P-channel MOSFET, with continuous drain current of -1.9 A at Ta=25℃ and pulsed drain current of -7.6 A.
3 Drain passive Drain terminal of the P-channel MOSFET, with drain-source voltage rating of -60 V and RDS(on) of 170 mΩ typ and 215 mΩ max at VGS = -10 V.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: S-LP2309LT1G
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: s-lp2309lt1g-etched.step / s-lp2309lt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); s-lp2309lt1g.step / s-lp2309lt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (6 pp, sha256 8adce3d07547c6fd, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF