component
74HCT595PW
Public Made by Adomby adom
Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HCT595PW
Nexperia · Shift Registers · TSSOP-16
74HCT595PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | tri_state | Parallel data output 1; a 3-state output that goes to high-impedance OFF-state when OE is HIGH. |
| 2 | Q2 | tri_state | Parallel data output 2; a 3-state output that goes to high-impedance OFF-state when OE is HIGH. |
| 3 | Q3 | tri_state | Parallel data output 3; a 3-state output that goes to high-impedance OFF-state when OE is HIGH. |
| 4 | Q4 | tri_state | Parallel data output 4; a 3-state output that goes to high-impedance OFF-state when OE is HIGH. |
| 5 | Q5 | tri_state | Parallel data output 5; a 3-state output that goes to high-impedance OFF-state when OE is HIGH. |
| 6 | Q6 | tri_state | Parallel data output 6; a 3-state output that goes to high-impedance OFF-state when OE is HIGH. |
| 7 | Q7 | tri_state | Parallel data output 7; a 3-state output that goes to high-impedance OFF-state when OE is HIGH. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 9 | Q7S | output | Serial data output that carries the shift register contents out to cascade additional devices. |
| 10 | MR | input | Master reset, active LOW; a LOW level resets the shift register. |
| 11 | SHCP | input | Shift register clock input; data is shifted in on each LOW-to-HIGH transition. |
| 12 | STCP | input | Storage register clock input; a LOW-to-HIGH transition transfers the shift register contents to the storage register. |
| 13 | OE | input | Output enable input, active LOW; a HIGH level forces the parallel outputs Qn into high-impedance OFF-state without changing the registers. |
| 14 | DS | input | Serial data input to the 8-bit shift register. |
| 15 | Q0 | tri_state | Parallel data output 0; a 3-state output that goes to high-impedance OFF-state when OE is HIGH. |
| 16 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for 74HC595 and 4.5 V to 5.5 V for 74HCT595 per the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 6 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 6 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 6 | |
| Output current, pin Q7S | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V); pin Q7S | 6 | |
| Output current, pins Qn | IO | -35 | 35 | mA | VO = -0.5 V to (VCC + 0.5 V); pins Qn | 6 | |
| Supply current | ICC | 70 | mA | 6 | |||
| Ground current | IGND | -70 | mA | 6 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| Total power dissipation | Ptot | 500 | mW | SOT403-1 (TSSOP16); derates 8.5 mW/K above 91 °C | 6 | ||
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 7 | |
| Input voltage | VI | 0 | V | 7 | |||
| Output voltage | VO | 0 | V | 7 | |||
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 7 | |
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 7 | |
| HIGH-level input voltage | VIH | 2 | 1.6 | V | VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 8 | |
| LOW-level input voltage | VIL | 1.2 | 0.8 | V | VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 8 | |
| HIGH-level output voltage, all outputs | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +85 °C | 8 | |
| HIGH-level output voltage, Q7S | VOH | 3.84 | 4.32 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4 mA; -40 °C to +85 °C | 8 | |
| HIGH-level output voltage, Q7S | VOH | 3.7 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4 mA; -40 °C to +125 °C | 8 | ||
| HIGH-level output voltage, Qn bus drivers | VOH | 3.7 | 4.32 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -6 mA; -40 °C to +85 °C | 8 | |
| LOW-level output voltage, all outputs | VOL | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +85 °C | 8 | |
| LOW-level output voltage, Q7S | VOL | 0.15 | 0.33 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; -40 °C to +85 °C | 8 | |
| LOW-level output voltage, Q7S | VOL | 0.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; -40 °C to +125 °C | 8 | ||
| LOW-level output voltage, Qn bus drivers | VOL | 0.16 | 0.33 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 6.0 mA; -40 °C to +85 °C | 8 | |
| LOW-level output voltage, Qn bus drivers | VOL | 0.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 6.0 mA; -40 °C to +125 °C | 8 | ||
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 5.5 V | 9 | |
| OFF-state output current | IOZ | -5 | 5 | μA | VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; -40 °C to +85 °C | 9 | |
| OFF-state output current | IOZ | -10 | 10 | μA | VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND; -40 °C to +125 °C | 9 | |
| Supply current | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +85 °C | 9 | ||
| Supply current | ICC | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 9 | ||
| Additional supply current, pins MR, SHCP, STCP, OE | ΔICC | 150 | 675 | μA | per input pin; other inputs at VCC or GND; IO = 0 A; VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 9 | |
| Additional supply current, pins MR, SHCP, STCP, OE | ΔICC | 735 | μA | per input pin; other inputs at VCC or GND; IO = 0 A; VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 9 | ||
| Additional supply current, pin DS | ΔICC | 25 | 113 | μA | per input pin; other inputs at VCC or GND; IO = 0 A; VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 9 | |
| Additional supply current, pin DS | ΔICC | 123 | μA | per input pin; other inputs at VCC or GND; IO = 0 A; VI = VCC - 2.1 V; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 9 | ||
| Propagation delay SHCP to Q7S | tpd | 25 | 42 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 6 | 11 | |
| Propagation delay SHCP to Q7S | tpd | 63 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 6 | 11 | ||
| Propagation delay STCP to Qn | tpd | 24 | 40 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 7 | 11 | |
| Propagation delay STCP to Qn | tpd | 60 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 7 | 11 | ||
| HIGH to LOW propagation delay MR to Q7S | tPHL | 23 | 40 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 9 | 11 | |
| HIGH to LOW propagation delay MR to Q7S | tPHL | 60 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 9 | 11 | ||
| Enable time OE to Qn | ten | 21 | 35 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 10 | 11 | |
| Enable time OE to Qn | ten | 53 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 10 | 11 | ||
| Disable time OE to Qn | tdis | 18 | 30 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 10 | 11 | |
| Disable time OE to Qn | tdis | 45 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 10 | 11 | ||
| Pulse width SHCP HIGH or LOW | tW | 16 | 6 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 6 | 11 | |
| Pulse width SHCP HIGH or LOW | tW | 24 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 6 | 11 | ||
| Pulse width STCP HIGH or LOW | tW | 16 | 5 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 7 | 11 | |
| Pulse width STCP HIGH or LOW | tW | 24 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 7 | 11 | ||
| Pulse width MR LOW | tW | 20 | 8 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 9 | 11 | |
| Pulse width MR LOW | tW | 30 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 9 | 11 | ||
| Set-up time DS to SHCP | tsu | 16 | 5 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 8 | 11 | |
| Set-up time DS to SHCP | tsu | 24 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 8 | 11 | ||
| Set-up time SHCP to STCP | tsu | 16 | 8 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 8 | 11 | |
| Set-up time SHCP to STCP | tsu | 24 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 8 | 11 | ||
| Hold time DS to SHCP | th | 3 | -2 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 8 | 11 | |
| Hold time DS to SHCP | th | 3 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 8 | 11 | ||
| Recovery time MR to SHCP | trec | 10 | -7 | ns | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 9 | 11 | |
| Recovery time MR to SHCP | trec | 15 | ns | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 9 | 11 | ||
| Maximum frequency SHCP and STCP | fmax | 30 | 52 | MHz | VCC = 4.5 V to 5.5 V; 25 °C; see Fig. 6 and Fig. 7 | 11 | |
| Maximum frequency SHCP and STCP | fmax | 20 | MHz | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C; see Fig. 6 and Fig. 7 | 11 |
CAD (KiCad official)
- Symbol:
74HCT595PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74hct595pw-etched.step/74hct595pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hct595pw.step/74hct595pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (21 pp, sha256
fa24207e780cd8c4, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).