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74HC4094PW-Q100J

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Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74HC4094PW-Q100J

Nexperia · Shift Registers · TSSOP-16

74HC4094PW-Q100J from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 STR input Strobe input; when HIGH, the data in the shift register is transferred to the storage register.
2 D input Serial data input to the 8-stage shift register, clocked in on the LOW-to-HIGH transitions of CP.
3 CP input Clock input; data is shifted on LOW-to-HIGH transitions and the storage register is not affected by CP alone.
4 QP0 tri_state Parallel 3-state output of storage register stage 0, high-impedance OFF-state when OE is LOW.
5 QP1 tri_state Parallel 3-state output of storage register stage 1, high-impedance OFF-state when OE is LOW.
6 QP2 tri_state Parallel 3-state output of storage register stage 2, high-impedance OFF-state when OE is LOW.
7 QP3 tri_state Parallel 3-state output of storage register stage 3, high-impedance OFF-state when OE is LOW.
8 GND power_in Ground supply voltage (0 V reference for all voltages).
9 QS1 output Serial output that presents shift register stage 7 data on LOW-to-HIGH CP transitions, for cascading with fast clock edges.
10 QS2 output Serial output that presents the same data as QS1 on the next HIGH-to-LOW CP transition, for cascading with slow clock edges.
11 QP7 tri_state Parallel 3-state output of storage register stage 7, high-impedance OFF-state when OE is LOW.
12 QP6 tri_state Parallel 3-state output of storage register stage 6, high-impedance OFF-state when OE is LOW.
13 QP5 tri_state Parallel 3-state output of storage register stage 5, high-impedance OFF-state when OE is LOW.
14 QP4 tri_state Parallel 3-state output of storage register stage 4, high-impedance OFF-state when OE is LOW.
15 OE input Output enable input; outputs show storage register data when HIGH and go to high-impedance OFF-state when LOW, without affecting the registers.
16 VCC power_in Supply voltage; 2.0 V to 6.0 V for 74HC4094-Q100 and 4.5 V to 5.5 V for 74HCT4094-Q100 (recommended operating range).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 5
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 5
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 5
output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 5
supply current ICC 50 mA 5
ground current IGND -50 mA 5
storage temperature Tstg -65 150 °C 5
total power dissipation Ptot 500 mW [1] SOT403-1 (TSSOP16): derates linearly 8.5 mW/K above 91 °C 5
supply voltage VCC 2 5 6 V 74HC4094-Q100 5
input voltage VI 0 V 5
output voltage VO 0 V 5
ambient temperature Tamb -40 25 125 °C 5
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 5
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 5
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 5
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V 6
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V 6
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V 6
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V 6
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V 6
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V 6
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V 6
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V 6
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V 6
HIGH-level output voltage VOH 5.2 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V 6
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V 6
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V 6
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 6
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V 6
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 6
propagation delay CP to QS1 tpd 50 225 ns CP to QS1; see Fig. 6; VCC = 2.0 V 8
propagation delay CP to QS1 tpd 18 45 ns CP to QS1; see Fig. 6; VCC = 4.5 V 8
propagation delay CP to QS1 tpd 14 38 ns CP to QS1; see Fig. 6; VCC = 6.0 V 8
propagation delay CP to QS2 tpd 44 205 ns CP to QS2; see Fig. 6; VCC = 2.0 V 8
propagation delay CP to QS2 tpd 16 41 ns CP to QS2; see Fig. 6; VCC = 4.5 V 8
propagation delay CP to QS2 tpd 13 35 ns CP to QS2; see Fig. 6; VCC = 6.0 V 8
propagation delay CP to QPn tpd 63 295 ns CP to QPn; see Fig. 6; VCC = 2.0 V 8
propagation delay CP to QPn tpd 23 59 ns CP to QPn; see Fig. 6; VCC = 4.5 V 8
propagation delay CP to QPn tpd 18 50 ns CP to QPn; see Fig. 6; VCC = 6.0 V 8
propagation delay STR to QPn tpd 58 270 ns STR to QPn; see Fig. 7; VCC = 2.0 V 8
propagation delay STR to QPn tpd 21 54 ns STR to QPn; see Fig. 7; VCC = 4.5 V 8
propagation delay STR to QPn tpd 17 46 ns STR to QPn; see Fig. 7; VCC = 6.0 V 8
enable time OE to QPn ten 55 265 ns OE to QPn; see Fig. 8; VCC = 2.0 V 8
enable time OE to QPn ten 20 53 ns OE to QPn; see Fig. 8; VCC = 4.5 V 8
enable time OE to QPn ten 16 45 ns OE to QPn; see Fig. 8; VCC = 6.0 V 8
disable time OE to QPn tdis 41 190 ns OE to QPn; see Fig. 8; VCC = 2.0 V 8
disable time OE to QPn tdis 15 38 ns OE to QPn; see Fig. 8; VCC = 4.5 V 8
disable time OE to QPn tdis 12 32 ns OE to QPn; see Fig. 8; VCC = 6.0 V 8
transition time QPn and QSn tt 19 110 ns QPn and QSn; see Fig. 6; VCC = 2.0 V 8
transition time QPn and QSn tt 7 22 ns QPn and QSn; see Fig. 6; VCC = 4.5 V 8
transition time QPn and QSn tt 6 19 ns QPn and QSn; see Fig. 6; VCC = 6.0 V 8
maximum frequency CP fmax 4 28 MHz CP; see Fig. 6; VCC = 2.0 V 9
maximum frequency CP fmax 20 87 MHz CP; see Fig. 6; VCC = 4.5 V 9
maximum frequency CP fmax 24 103 MHz CP; see Fig. 6; VCC = 6.0 V 9

CAD (KiCad official)

  • Symbol: 74HC4094PW-Q100J
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc4094pw-q100j-etched.step / 74hc4094pw-q100j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc4094pw-q100j.step / 74hc4094pw-q100j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 9365a6b13f483263, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF