component
74FCT3245APGG
Public Made by Adomby adom
RENESAS Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdown74FCT3245APGG
RENESAS · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
74FCT3245APGG from RENESAS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIR | input | Direction control input: LOW selects Bus B data to Bus A, HIGH selects Bus A data to Bus B. |
| 2 | A1 | bidirectional | Side A input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 3 | A2 | bidirectional | Side A input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 4 | A3 | bidirectional | Side A input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 5 | A4 | bidirectional | Side A input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 6 | A5 | bidirectional | Side A input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 7 | A6 | bidirectional | Side A input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 8 | A7 | bidirectional | Side A input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 9 | A8 | bidirectional | Side A input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | B8 | bidirectional | Side B input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 12 | B7 | bidirectional | Side B input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 13 | B6 | bidirectional | Side B input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 14 | B5 | bidirectional | Side B input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 15 | B4 | bidirectional | Side B input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 16 | B3 | bidirectional | Side B input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 17 | B2 | bidirectional | Side B input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 18 | B1 | bidirectional | Side B input or 3-state output; direction set by DIR and disabled to High Z when OE is HIGH. |
| 19 | OE | input | 3-state output enable input, active LOW; HIGH disables both ports to High Z. |
| 20 | VCC | power_in | Supply voltage: 3.3V ±0.3V (normal range) or 2.7V to 3.6V (extended range). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Terminal Voltage with Respect to GND (VCC terminals) | VTERM(2) | -0.5 | 4.6 | V | VCC terminals | 2 | |
| Terminal Voltage with Respect to GND (Input terminals) | VTERM(3) | -0.5 | 7 | V | Input terminals | 2 | |
| Terminal Voltage with Respect to GND (Outputs and I/O terminals) | VTERM(4) | -0.5 | V | Outputs and I/O terminals; upper limit printed as VCC+0.5 V | 2 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 2 | ||
| DC Output Current | IOUT | -60 | 60 | mA | 2 | ||
| Ambient Operating Temperature (Industrial) | TA | -40 | 85 | °C | Industrial range; following conditions apply unless otherwise specified | 3 | |
| Supply Voltage (Extended Range) | VCC | 2.7 | 3.6 | V | VCC = 2.7V to 3.6V, Extended Range | 3 | |
| Supply Voltage (Normal Range, 3.3V ±0.3V) | VCC | -0.3 | 3.3 | 0.3 | V | Normal Range, VCC = 3.3V ±0.3V | 1 |
| Input Capacitance | CIN | 3.5 | 6 | pF | VIN = 0V; TA = +25°C, F = 1.0MHz | 2 | |
| Output Capacitance | COUT | 4 | 8 | pF | VOUT = 0V; TA = +25°C, F = 1.0MHz | 2 | |
| Input HIGH Level (Input pins) | VIH | 2 | 5.5 | V | Guaranteed Logic HIGH Level | 3 | |
| Input HIGH Level (I/O pins) | VIH | 2 | V | Guaranteed Logic HIGH Level; upper limit printed as Vcc+0.5 V | 3 | ||
| Input LOW Level (Input and I/O pins) | VIL | -0.5 | 0.8 | V | Guaranteed Logic LOW Level | 3 | |
| Input HIGH Current (Input pins) | IIH | -1 | 1 | µA | VCC = Max., VI = 5.5V | 3 | |
| Input HIGH Current (I/O pins) | IIH | -1 | 1 | µA | VI = VCC | 3 | |
| Input LOW Current (Input pins) | IIL | -1 | 1 | µA | VI = GND | 3 | |
| Input LOW Current (I/O pins) | IIL | -1 | 1 | µA | VI = GND | 3 | |
| High Impedance Output Current (3-State output pins) | IOZH | -1 | 1 | µA | VCC = Max., VO = VCC | 3 | |
| Clamp Diode Voltage | VIK | -0.7 | -1.2 | V | VCC = Min., IIN = -18mA | 3 | |
| Output HIGH Current | IODH | -36 | -60 | -110 | mA | VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V | 3 |
| Output LOW Current | IODL | 50 | 90 | 200 | mA | VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V | 3 |
| Output HIGH Voltage | VOH | 2.4 | 3 | V | VCC = Min., VIN = VIH or VIL, IOH = -3mA | 3 | |
| Output LOW Voltage | VOL | 0.2 | V | VCC = Min., VIN = VIH or VIL, IOL = 0.1mA | 3 | ||
| Output LOW Voltage | VOL | 0.2 | 0.4 | V | VCC = Min., VIN = VIH or VIL, IOL = 16mA | 3 | |
| Output LOW Voltage | VOL | 0.3 | 0.55 | V | VCC = Min., VIN = VIH or VIL, IOL = 24mA | 3 | |
| Output LOW Voltage | VOL | 0.3 | 0.5 | V | VCC = 3V, VIN = VIH or VIL, IOL = 24mA | 3 | |
| Short Circuit Current | IOS | -60 | -135 | -240 | mA | VCC = Max., VO = GND | 3 |
| Input Hysteresis | VH | 150 | mV | 3 | |||
| Quiescent Power Supply Current | ICCL, ICCH, ICCZ | 0.1 | 10 | µA | VCC = Max., VIN = GND or VCC | 3 | |
| Quiescent Power Supply Current | ICC | 2 | 30 | µA | VCC = Max., VIN = VCC - 0.6V | 4 | |
| Dynamic Power Supply Current | ICCD | 60 | 85 | µA/MHz | VCC = Max., VIN = VCC or GND, outputs open, OE = DIR = GND, one input toggling, 50% duty cycle | 4 | |
| Total Power Supply Current | IC | 0.6 | 0.9 | mA | VCC = Max., VIN = VCC, VIN = GND, outputs open, fI = 10MHz, 50% duty cycle, OE = DIR = GND | 4 | |
| Total Power Supply Current | IC | 1.2 | 1.7 | mA | VCC = Max., VIN = VCC, VIN = GND, outputs open, fI = 2.5MHz, 50% duty cycle, OE = DIR = GND | 4 | |
| Total Power Supply Current | IC | 1.2 | 1.8 | mA | VCC = Max., VIN = VCC - 0.6V, VIN = GND, outputs open, fI = 2.5MHz, 50% duty cycle, OE = DIR = GND | 4 | |
| Propagation Delay (A to B, B to A) | tPLH, tPHL | 1.5 | 4.6 | ns | CL = 50pF, RL = 500Ω | 4 | |
| Output Enable Time (OE to A or B) | tPZH, tPZL | 1.5 | 6.2 | ns | CL = 50pF, RL = 500Ω | 4 | |
| Output Disable Time (OE to A or B) | tPHZ, tPLZ | 1.5 | 5 | ns | CL = 50pF, RL = 500Ω | 4 | |
| Output Enable Time (DIR to A or B) | tPZH, tPZL | 1.5 | 6.2 | ns | CL = 50pF, RL = 500Ω | 4 | |
| Output Disable Time (DIR to A or B) | tPHZ, tPLZ | 1.5 | 5 | ns | CL = 50pF, RL = 500Ω | 4 |
CAD (KiCad official)
- Symbol:
74FCT3245APGG - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
74fct3245apgg-etched.step/74fct3245apgg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74fct3245apgg.step/74fct3245apgg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (7 pp, sha256
f173f611fcc52e6a, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).